9bf78f0866
2. Remove the now redundant 32 to 64 register mapping for mp_size_t inputs in Windows assembler
139 lines
3.1 KiB
NASM
139 lines
3.1 KiB
NASM
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; Verdxon 1.1.4.
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;
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; Copyright 2008 Jason Moxham
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;
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; Windows Conversion Copyright 2008 Brian Gladman
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;
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; This file is part of the MPIR Library.
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;
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; The MPIR Library is free software; you can redistribute it and/or modify
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; it under the terms of the GNU Lesser General Public License as published
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; by the Free Software Foundation; either verdxon 2.1 of the License, or (at
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; your option) any later verdxon.
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; The MPIR Library is distributed in the hope that it will be useful, but
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; WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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; License for more details.
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;
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; You should have received a copy of the GNU Lesser General Public License
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; along with the MPIR Library; see the file COPYING.LIB. If not, write
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; to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
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; Boston, MA 02110-1301, USA.
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;
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; mp_limb_t mpn_rshift(mp_ptr, mp_ptr, mp_size_t, mp_uint)
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; rax rdi rsi rdx rcx
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; rax rcx rdx r8 r9d
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%include "..\yasm_mac.inc"
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CPU Athlon64
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BITS 64
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LEAF_PROC mpn_rshift
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mov r9d, r9d
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movq mm0, r9
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mov rax, 64
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sub rax, r9
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movq mm1, rax
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mov rax, r8
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mov r8, 4
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lea rdx, [rdx+rax*8-32]
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lea rcx, [rcx+rax*8-32]
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sub r8, rax
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movq mm5, [rdx+r8*8]
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movq mm3, mm5
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psllq mm5, mm1
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movq rax, mm5
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psrlq mm3, mm0
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jge .2
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xalign 16
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.1: movq mm2, [rdx+r8*8+8]
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movq mm4, mm2
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psllq mm2, mm1
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por mm3, mm2
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movq [rcx+r8*8], mm3
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psrlq mm4, mm0
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movq mm5, [rdx+r8*8+16]
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movq mm3, mm5
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psllq mm5, mm1
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por mm4, mm5
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movq [rcx+r8*8+8], mm4
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psrlq mm3, mm0
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movq mm2, [rdx+r8*8+24]
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movq mm4, mm2
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psllq mm2, mm1
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por mm3, mm2
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movq mm5, [rdx+r8*8+32]
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movq [rcx+r8*8+16], mm3
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psrlq mm4, mm0
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movq mm3, mm5
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psllq mm5, mm1
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por mm4, mm5
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movq [rcx+r8*8+24], mm4
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psrlq mm3, mm0
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add r8, 4
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jnc .1
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.2: cmp r8, 2
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ja .6
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jz .5
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jp .4
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.3: movq mm2, [rdx+r8*8+8]
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movq mm4, mm2
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psllq mm2, mm1
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por mm3, mm2
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movq [rcx+r8*8], mm3
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psrlq mm4, mm0
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movq mm5, [rdx+r8*8+16]
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movq mm3, mm5
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psllq mm5, mm1
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por mm4, mm5
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movq [rcx+r8*8+8], mm4
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psrlq mm3, mm0
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movq mm2, [rdx+r8*8+24]
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movq mm4, mm2
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psllq mm2, mm1
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por mm3, mm2
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movq [rcx+r8*8+16], mm3
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psrlq mm4, mm0
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movq [rcx+r8*8+24], mm4
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emms
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ret
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xalign 16
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.4: movq mm2, [rdx+r8*8+8]
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movq mm4, mm2
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psllq mm2, mm1
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por mm3, mm2
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movq [rcx+r8*8], mm3
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psrlq mm4, mm0
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movq mm5, [rdx+r8*8+16]
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movq mm3, mm5
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psllq mm5, mm1
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por mm4, mm5
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movq [rcx+r8*8+8], mm4
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psrlq mm3, mm0
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movq [rcx+r8*8+16], mm3
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emms
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ret
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xalign 16
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.5: movq mm2, [rdx+r8*8+8]
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movq mm4, mm2
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psllq mm2, mm1
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por mm3, mm2
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movq [rcx+r8*8], mm3
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psrlq mm4, mm0
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movq [rcx+r8*8+8], mm4
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emms
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ret
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xalign 16
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.6: movq [rcx+r8*8], mm3
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emms
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ret
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win64_gcc_end |