234 lines
6.5 KiB
C
234 lines
6.5 KiB
C
/*
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Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006
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Free Software Foundation, Inc.
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Copyright 2008 William Hart.
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Copyright 2009,2010,2011 Jason Moxham
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Copyright 2010 Gonzalo Tornaria
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This file is part of the MPIR Library.
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The MPIR Library is free software; you can redistribute it and/or modify
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it under the terms of the GNU Lesser General Public License as published
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by the Free Software Foundation; either version 2.1 of the License, or (at
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your option) any later version.
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The MPIR Library is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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License for more details.
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You should have received a copy of the GNU Lesser General Public License
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along with the MPIR Library; see the file COPYING.LIB. If not, write
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to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
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Boston, MA 02110-1301, USA.
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*/
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#define WANT_FAKE_BUILD_CPU 0
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#define WANT_FAKE_FAT_CPU 0
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#define FAKE_BUILD_CPU_VENDOR "MPIRSNOTFAKE"
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#define FAKE_BUILD_CPU_FAMILY 0
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#define FAKE_BUILD_CPU_EXTFAMILY 0
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#define FAKE_BUILD_CPU_MODEL 0
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#define FAKE_BUILD_CPU_EXTMODEL 0
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#define FAKE_FAT_CPU_VENDOR "MPIRSNOTFAKE"
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#define FAKE_FAT_CPU_FAMILY 0
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#define FAKE_FAT_CPU_EXTFAMILY 0
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#define FAKE_FAT_CPU_MODEL 0
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#define FAKE_FAT_CPU_EXTMODEL 0
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#if INFAT
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#define WANT_FAKE_CPU WANT_FAKE_FAT_CPU
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#define FAKE_CPU_VENDOR FAKE_FAT_CPU_VENDOR
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#define FAKE_CPU_FAMILY FAKE_FAT_CPU_FAMILY
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#define FAKE_CPU_EXTFAMILY FAKE_FAT_CPU_EXTFAMILY
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#define FAKE_CPU_MODEL FAKE_FAT_CPU_MODEL
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#define FAKE_CPU_EXTMODEL FAKE_FAT_CPU_EXTMODEL
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#endif
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#if CONFIG_GUESS
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#define WANT_FAKE_CPU WANT_FAKE_BUILD_CPU
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#define FAKE_CPU_VENDOR FAKE_BUILD_CPU_VENDOR
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#define FAKE_CPU_FAMILY FAKE_BUILD_CPU_FAMILY
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#define FAKE_CPU_EXTFAMILY FAKE_BUILD_CPU_EXTFAMILY
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#define FAKE_CPU_MODEL FAKE_BUILD_CPU_MODEL
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#define FAKE_CPU_EXTMODEL FAKE_BUILD_CPU_EXTMODEL
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#endif
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#if WANT_FAKE_CPU
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long fake_cpuid(char *p,unsigned int level)
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{unsigned int eax,feat801=0,feat2=0,family,extfamily,model,extmodel;
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char *vendor;
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// can set feat801=1 for netburstlahf
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// can set feat2=256 for prescott
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vendor=FAKE_CPU_VENDOR;
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family=FAKE_CPU_FAMILY;
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extfamily=FAKE_CPU_EXTFAMILY;
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model=FAKE_CPU_MODEL;
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extmodel=FAKE_CPU_EXTMODEL;
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memset(p,0,12);
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if(level==0){strncpy(p,vendor,12);return 1;}
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if(level==1){eax=0+(model<<4)+(family<<8)+(0<<12)+(extmodel<<16)+(extfamily<<20);memcpy(p,&feat2,4);return eax;}
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if(level==0x80000000){return 1;}
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if(level==0x80000001){memcpy(p+8,&feat801,4);return 0;}
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return 0;}
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#endif
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#if WANT_FAKE_CPU
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#define __gmpn_cpuid fake_cpuid
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#else
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#if CONFIG_GUESS
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#define __gmpn_cpuid(_x,_y) cpuid(_x,_y,1,0,0)
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#endif
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#endif
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#if CONFIG_GUESS
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// use's the stringinzing directive #x ie #x expands to "x"
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#define CPUIS(x) modelstr=#x
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char* __gmpn_cpu(int *vector){
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#endif
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#if INFAT
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#define CPUIS(x) do{TRACE(printf(" "#x"\n"));CPUSETUP_##x;}while(0)
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char* __gmpn_cpu(struct cpuvec_t *vector){
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struct cpuvec_t decided_cpuvec;
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#endif
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char vendor_string[13];
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char features[12];
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long fms;
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int family, model, stepping,feat;
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char *modelstr=0;
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#if INFAT
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memset (&decided_cpuvec, '\0', sizeof (decided_cpuvec));
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CPUVEC_SETUP_fat;
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#if FAT32
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CPUVEC_SETUP_x86;
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#endif
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#if FAT64
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CPUVEC_SETUP_x86_64;
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#endif
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#endif
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__gmpn_cpuid (vendor_string, 0);
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vendor_string[12] = 0;
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fms = __gmpn_cpuid (features, 1);
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family = ((fms >> 8) & 15) + ((fms >> 20) & 0xff);
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model = ((fms >> 4) & 15) + ((fms >> 12) & 0xf0);
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stepping = fms & 15;
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#if CONFIG_GUESS_64BIT
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modelstr = "x86_64";
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#else
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modelstr = "i486";// shouldn't we make this x86??
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#endif
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if (strcmp (vendor_string, "GenuineIntel") == 0)
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{
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switch (family)
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{
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#if CONFIG_GUESS_32BIT || FAT32
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case 5:
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if (model <= 2) CPUIS(pentium);
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if (model >= 4) CPUIS(pentiummmx);
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break;
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#endif
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case 6:
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#if CONFIG_GUESS_32BIT || FAT32
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if (model == 1) { CPUIS(pentiumpro);break;}
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if (model <= 6) { CPUIS(pentium2);break;}
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if (model <= 13){ CPUIS(pentium3);break;}
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if (model == 14){ CPUIS(core);break;}
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#endif
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if (model == 15){ CPUIS(core2);break;}
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if (model == 22){ CPUIS(core2);break;}
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if (model == 23){ CPUIS(penryn);break;}
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if (model == 26){ CPUIS(nehalem);break;}
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if (model == 28){ CPUIS(atom);break;}
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if (model == 29){ CPUIS(penryn);break;}
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if (model == 30){ CPUIS(nehalem);break;}
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if (model == 31){ CPUIS(nehalem);break;}
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if (model == 37){ CPUIS(westmere);break;}
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if (model == 42){ CPUIS(sandybridge);break;}
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if (model == 44){ CPUIS(westmere);break;}
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if (model == 45){ CPUIS(sandybridge);break;} // check this model is correct
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if (model == 46){ CPUIS(nehalem);break;}
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if (model == 47){ CPUIS(westmere);break;}
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break;
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case 15:
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#if CONFIG_GUESS_64BIT || FAT64
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__gmpn_cpuid(features,0x80000001);
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if ( features[8]&1 ){ CPUIS(netburstlahf);break;}
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CPUIS(netburst);break;
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#endif
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#if CONFIG_GUESS_32BIT || FAT32
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if (model <= 6) { CPUIS(pentium4);break;}
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feat = ((int *)features)[2];
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if (feat & 1) { CPUIS(prescott);break;}
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#endif
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break;
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}
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}
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else if (strcmp (vendor_string, "AuthenticAMD") == 0)
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{
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switch (family)
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{
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#if CONFIG_GUESS_32BIT || FAT32
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case 5:
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if (model <= 3) { CPUIS(k5);break;}
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if (model <= 7) { CPUIS(k6);break;}
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if (model <= 8) { CPUIS(k62);break;}
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if (model <= 9) { CPUIS(k63);break;}
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break;
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case 6:
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CPUIS(k7);
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break;
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#endif
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case 15:
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CPUIS(k8);
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break;
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case 16:
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if (model == 2) { CPUIS(k10);break;}
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if (model == 4) { CPUIS(k102);break;}
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if (model == 5) { CPUIS(k102);break;}
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if (model == 6) { CPUIS(k102);break;}
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if (model == 8) { CPUIS(k102);break;}
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if (model == 9) { CPUIS(k102);break;}
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if (model == 10) { CPUIS(k102);break;}
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break;
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case 17:
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CPUIS(k8);// fusion of K8 and GPU
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break;
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case 18:
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CPUIS(k103);// like k102 but with hardware divider , is this lano?
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break;
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case 20:
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CPUIS(bobcat);// fusion of bobcat and GPU
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break;
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case 21:
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CPUIS(bulldozer);
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break;
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}
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}
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else if (strcmp (vendor_string, "CentaurHauls") == 0)
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{
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switch (family)
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{
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case 6:
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if (model == 15){CPUIS(nano);break;}
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#if CONFIG_GUESS_32BIT || FAT32
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if (model < 9) { CPUIS(viac3);break;}
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CPUIS(viac32);break;
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#endif
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}
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}
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#if INFAT
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*vector=decided_cpuvec;
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#endif
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return modelstr;}
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