134 lines
5.6 KiB
C
134 lines
5.6 KiB
C
/* longlong.h -- definitions for mixed size 32/64 bit arithmetic.
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Copyright 1991, 1992, 1993, 1994, 1996, 1997, 1999, 2000, 2001, 2002, 2003,
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2004, 2005 Free Software Foundation, Inc.
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This file is free software; you can redistribute it and/or modify
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it under the terms of the GNU Lesser General Public License as published by
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the Free Software Foundation; either version 2.1 of the License, or (at your
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option) any later version.
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This file is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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License for more details.
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You should have received a copy of the GNU Lesser General Public License
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along with this file; see the file COPYING.LIB. If not, write to
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the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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MA 02110-1301, USA. */
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#if defined (__GNUC__)
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#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
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do { \
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if (__builtin_constant_p (bh) && (bh) == 0) \
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__asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{aze|addze} %0,%2" \
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: "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
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else if (__builtin_constant_p (bh) && (bh) == ~(USItype) 0) \
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__asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{ame|addme} %0,%2" \
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: "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
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else \
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__asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3" \
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: "=r" (sh), "=&r" (sl) \
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: "r" (ah), "r" (bh), "%r" (al), "rI" (bl)); \
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} while (0)
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#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
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do { \
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if (__builtin_constant_p (ah) && (ah) == 0) \
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__asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfze|subfze} %0,%2" \
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: "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
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else if (__builtin_constant_p (ah) && (ah) == ~(USItype) 0) \
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__asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfme|subfme} %0,%2" \
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: "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
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else if (__builtin_constant_p (bh) && (bh) == 0) \
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__asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{ame|addme} %0,%2" \
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: "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
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else if (__builtin_constant_p (bh) && (bh) == ~(USItype) 0) \
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__asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{aze|addze} %0,%2" \
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: "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
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else \
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__asm__ ("{sf%I4|subf%I4c} %1,%5,%4\n\t{sfe|subfe} %0,%3,%2" \
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: "=r" (sh), "=&r" (sl) \
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: "r" (ah), "r" (bh), "rI" (al), "r" (bl)); \
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} while (0)
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#define count_leading_zeros(count, x) \
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__asm__ ("{cntlz|cntlzw} %0,%1" : "=r" (count) : "r" (x))
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#define COUNT_LEADING_ZEROS_0 32
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#if HAVE_HOST_CPU_FAMILY_powerpc
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#define umul_ppmm(ph, pl, m0, m1) \
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do { \
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USItype __m0 = (m0), __m1 = (m1); \
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__asm__ ("mulhwu %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
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(pl) = __m0 * __m1; \
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} while (0)
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#define smul_ppmm(ph, pl, m0, m1) \
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do { \
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SItype __m0 = (m0), __m1 = (m1); \
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__asm__ ("mulhw %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
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(pl) = __m0 * __m1; \
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} while (0)
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#else
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#define smul_ppmm(xh, xl, m0, m1) \
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__asm__ ("mul %0,%2,%3" : "=r" (xh), "=q" (xl) : "r" (m0), "r" (m1))
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#define sdiv_qrnnd(q, r, nh, nl, d) \
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__asm__ ("div %0,%2,%4" : "=r" (q), "=q" (r) : "r" (nh), "1" (nl), "r" (d))
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#endif
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#endif
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/* 3 cycles on 604 or 750 since shifts and rlwimi's can pair. gcc (as of
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version 3.1 at least) doesn't seem to know how to generate rlwimi for
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anything other than bit-fields, so use "asm". */
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#if !defined(BSWAP_LIMB) && defined (__GNUC__) && HAVE_HOST_CPU_FAMILY_powerpc
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#define BSWAP_LIMB(dst, src) \
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do { \
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mp_limb_t __bswapl_src = (src); \
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mp_limb_t __tmp1 = __bswapl_src >> 24; /* low byte */ \
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mp_limb_t __tmp2 = __bswapl_src << 24; /* high byte */ \
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__asm__ ("rlwimi %0, %2, 24, 16, 23" /* 2nd low */ \
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: "=r" (__tmp1) : "0" (__tmp1), "r" (__bswapl_src)); \
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__asm__ ("rlwimi %0, %2, 8, 8, 15" /* 3nd high */ \
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: "=r" (__tmp2) : "0" (__tmp2), "r" (__bswapl_src)); \
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(dst) = __tmp1 | __tmp2; /* whole */ \
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} while (0)
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#endif
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/* Apparently lwbrx might be slow on some PowerPC chips, so restrict it to
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those we know are fast. */
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#if !defined(BSWAP_LIMB_FETCH) && defined (__GNUC__) && HAVE_LIMB_BIG_ENDIAN \
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&& (HAVE_HOST_CPU_powerpc604 \
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|| HAVE_HOST_CPU_powerpc604e \
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|| HAVE_HOST_CPU_powerpc750 \
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|| HAVE_HOST_CPU_powerpc7400)
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#define BSWAP_LIMB_FETCH(limb, src) \
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do { \
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mp_srcptr __blf_src = (src); \
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mp_limb_t __limb; \
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__asm__ ("lwbrx %0, 0, %1" \
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: "=r" (__limb) \
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: "r" (__blf_src), \
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"m" (*__blf_src)); \
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(limb) = __limb; \
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} while (0)
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#endif
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/* On the same basis that lwbrx might be slow, restrict stwbrx to those we
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know are fast. FIXME: Is this necessary? */
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#if !defined(BSWAP_LIMB_STORE) && defined (__GNUC__) && HAVE_LIMB_BIG_ENDIAN \
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&& (HAVE_HOST_CPU_powerpc604 \
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|| HAVE_HOST_CPU_powerpc604e \
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|| HAVE_HOST_CPU_powerpc750 \
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|| HAVE_HOST_CPU_powerpc7400)
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#define BSWAP_LIMB_STORE(dst, limb) \
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do { \
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mp_ptr __dst = (dst); \
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mp_limb_t __limb = (limb); \
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__asm__ ("stwbrx %1, 0, %2" \
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: "=m" (*__dst) \
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: "r" (__limb), \
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"r" (__dst)); \
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} while (0)
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#endif
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