166 lines
5.6 KiB
Plaintext
166 lines
5.6 KiB
Plaintext
Copyright 2000, 2001 Free Software Foundation, Inc.
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This file is part of the GNU MP Library.
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The GNU MP Library is free software; you can redistribute it and/or modify
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it under the terms of the GNU Lesser General Public License as published by
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the Free Software Foundation; either version 2.1 of the License, or (at your
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option) any later version.
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The GNU MP Library is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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License for more details.
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You should have received a copy of the GNU Lesser General Public License
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along with the GNU MP Library; see the file COPYING.LIB. If not, write to
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the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
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02110-1301, USA.
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AMD K7 MPN SUBROUTINES
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This directory contains code optimized for the AMD Athlon CPU.
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The mmx subdirectory has routines using MMX instructions. All Athlons have
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MMX, the separate directory is just so that configure can omit it if the
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assembler doesn't support MMX.
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STATUS
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Times for the loops, with all code and data in L1 cache.
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cycles/limb
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mpn_add/sub_n 1.6
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mpn_copyi 0.75 or 1.0 \ varying with data alignment
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mpn_copyd 0.75 or 1.0 /
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mpn_divrem_1 17.0 integer part, 15.0 fractional part
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mpn_mod_1 17.0
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mpn_divexact_by3 8.0
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mpn_l/rshift 1.2
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mpn_mul_1 3.4
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mpn_addmul/submul_1 3.9
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mpn_mul_basecase 4.42 cycles/crossproduct (approx)
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mpn_sqr_basecase 2.3 cycles/crossproduct (approx)
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or 4.55 cycles/triangleproduct (approx)
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Prefetching of sources hasn't yet been tried.
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NOTES
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cmov, MMX, 3DNow and some extensions to MMX and 3DNow are available.
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Write-allocate L1 data cache means prefetching of destinations is unnecessary.
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Floating point multiplications can be done in parallel with integer
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multiplications, but there doesn't seem to be any way to make use of this.
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Unsigned "mul"s can be issued every 3 cycles. This suggests 3 is a limit on
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the speed of the multiplication routines. The documentation shows mul
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executing in IEU0 (or maybe in IEU0 and IEU1 together), so it might be that,
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to get near 3 cycles code has to be arranged so that nothing else is issued
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to IEU0. A busy IEU0 could explain why some code takes 4 cycles and other
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apparently equivalent code takes 5.
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OPTIMIZATIONS
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Unrolled loops are used to reduce looping overhead. The unrolling is
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configurable up to 32 limbs/loop for most routines and up to 64 for some.
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The K7 has 64k L1 code cache so quite big unrolling is allowable.
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Computed jumps into the unrolling are used to handle sizes not a multiple of
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the unrolling. An attractive feature of this is that times increase
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smoothly with operand size, but it may be that some routines should just
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have simple loops to finish up, especially when PIC adds between 2 and 16
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cycles to get %eip.
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Position independent code is implemented using a call to get %eip for the
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computed jumps and a ret is always done, rather than an addl $4,%esp or a
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popl, so the CPU return address branch prediction stack stays synchronised
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with the actual stack in memory.
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Branch prediction, in absence of any history, will guess forward jumps are
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not taken and backward jumps are taken. Where possible it's arranged that
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the less likely or less important case is under a taken forward jump.
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CODING
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Instructions in general code have been shown grouped if they can execute
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together, which means up to three direct-path instructions which have no
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successive dependencies. K7 always decodes three and has out-of-order
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execution, but the groupings show what slots might be available and what
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dependency chains exist.
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When there's vector-path instructions an effort is made to get triplets of
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direct-path instructions in between them, even if there's dependencies,
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since this maximizes decoding throughput and might save a cycle or two if
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decoding is the limiting factor.
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INSTRUCTIONS
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adcl direct
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divl 39 cycles back-to-back
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lodsl,etc vector
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loop 1 cycle vector (decl/jnz opens up one decode slot)
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movd reg vector
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movd mem direct
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mull issue every 3 cycles, latency 4 cycles low word, 6 cycles high word
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popl vector (use movl for more than one pop)
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pushl direct, will pair with a load
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shrdl %cl vector, 3 cycles, seems to be 3 decode too
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xorl r,r false read dependency recognised
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REFERENCES
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"AMD Athlon Processor X86 Code Optimization Guide", AMD publication number
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22007, revision K, February 2002. Available on-line,
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http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/22007.pdf
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"3DNow Technology Manual", AMD publication number 21928G/0-March 2000.
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This describes the femms and prefetch instructions. Available on-line,
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http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/21928.pdf
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"AMD Extensions to the 3DNow and MMX Instruction Sets Manual", AMD
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publication number 22466, revision D, March 2000. This describes
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instructions added in the Athlon processor, such as pswapd and the extra
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prefetch forms. Available on-line,
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http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/22466.pdf
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"3DNow Instruction Porting Guide", AMD publication number 22621, revision B,
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August 1999. This has some notes on general Athlon optimizations as well as
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3DNow. Available on-line,
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http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/22621.pdf
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----------------
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Local variables:
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mode: text
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fill-column: 76
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End:
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