130 lines
4.5 KiB
Plaintext
130 lines
4.5 KiB
Plaintext
Copyright 2001, 2003, 2004 Free Software Foundation, Inc.
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This file is part of the GNU MP Library.
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The GNU MP Library is free software; you can redistribute it and/or modify
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it under the terms of the GNU Lesser General Public License as published by
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the Free Software Foundation; either version 2.1 of the License, or (at your
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option) any later version.
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The GNU MP Library is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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License for more details.
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You should have received a copy of the GNU Lesser General Public License
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along with the GNU MP Library; see the file COPYING.LIB. If not, write to
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the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
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02110-1301, USA.
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M68K MPN SUBROUTINES
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This directory contains mpn functions for various m68k family chips.
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CODE ORGANIZATION
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m68k m68000, m68010, m68060
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m68k/mc68020 m68020, m68030, m68040, and CPU32
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The m5200 "coldfire", which is m68000 less a few instructions, currently has
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no assembler code support.
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STATUS
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The code herein is old and poorly maintained. If somebody really cared, it
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could be optimized substantially. For example,
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* mpn_add_n and mpn_sub_n could, with more unrolling be improved from 6 to
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close to 4 c/l (on m68040).
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* The multiplication loops could be sped up by using the FPU.
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* mpn_lshift by 31 should use the special-case mpn_rshift by 1 code, and
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vice versa mpn_rshift by 31 use the special lshift by 1, when operand
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overlap permits.
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* On 68000, mpn_mul_1, mpn_addmul_1 and mpn_submul_1 could check for a
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16-bit multiplier and use two multiplies per limb, not four.
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Similarly various other _1 operations like mpn_mod_1, mpn_divrem_1,
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mpn_divexact_1, mpn_modexact_1c_odd.
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* On 68000, mpn_lshift and mpn_rshift could use a roll and mask instead of
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lsrl and lsll. This promises to be a speedup, effectively trading a 6+2*n
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shift for one or two 4 cycle masks. Suggested by Jean-Charles Meyrignac.
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* config.guess detects 68000, 68010, CPU32 and 68020 by running some code,
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but relies on system information for 030, 040 and 060. Can they be
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identified by running some code? Currently this only makes a difference
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to the compiler options selected, since we have no specific asm code for
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those chips.
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One novel idea for 68000 would be to use a 16-bit limb instead of 32-bits.
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This would suit the native 16x16 multiply, but might make it difficult to
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get full value from the native 32x32 add/sub/etc. This would be an ABI
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option, and would select "__GMP_SHORT_LIMB" in mpir.h.
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Naturally an entirely new set of asm subroutines would be needed for a
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16-bit limb. Also there's various places in the C code assuming limb>=long,
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which would need to be updated, eg. mpz_set_ui. Some of the nails changes
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may have helped cover some of this.
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ASM FILES
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The .asm files are put through m4 for macro processing, and with the help of
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configure give either MIT or Motorola syntax. The generic mpn/asm-defs.m4
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is used, together with mpn/m68k/m68k-defs.m4. See comments in those files.
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Not all possible syntax variations are covered. GCC config/m68k for
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instance has things like $ for immediates on CRDS or reversed cmp order for
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AT&T SGS. These could probably be handled if anyone really needs it.
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CALLING CONVENTIONS
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The SVR4 standard has an int of 32 bits, and all parameters 32-bit aligned
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on the stack.
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PalmOS and perhaps various embedded systems intended for 68000 however use
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an int of 16 bits and parameters only 16-bit aligned on the stack. This is
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generated by "gcc -mshort" (and is the default for the PalmOS gcc port, we
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believe).
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The asm files adapt to these two ABIs by checking sizeof(unsigned), coming
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through config.m4 as SIZEOF_UNSIGNED. Only mpn_lshift and mpn_rshift are
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affected, all other routines take longs and pointers, which are 32-bits in
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both cases.
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Strictly speaking the size of an int doesn't determine the stack padding
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convention. But if int is 16 bits then we can definitely say the host
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system is not SVR4, and therefore may as well assume we're in 16-bit stack
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alignment.
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REFERENCES
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"Motorola M68000 Family Programmer's Reference Manual", available online,
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http://e-www.motorola.com/brdata/PDFDB/docs/M68000PM.pdf
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"System V Application Binary Interface: Motorola 68000 Processor Family
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Supplement", AT&T, 1990, ISBN 0-13-877553-6. Has details of calling
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conventions and ELF style PIC coding.
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----------------
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Local variables:
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mode: text
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fill-column: 76
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End:
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