267 lines
6.8 KiB
NASM
267 lines
6.8 KiB
NASM
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; Copyright 2016 Jens Nurmann and Alexander Kruppa
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; This file is part of the MPIR Library.
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; The MPIR Library is free software; you can redistribute it and/or modify
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; it under the terms of the GNU Lesser General Public License as published
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; by the Free Software Foundation; either version 2.1 of the License, or (at
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; your option) any later version.
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; The MPIR Library is distributed in the hope that it will be useful, but
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; WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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; License for more details.
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; You should have received a copy of the GNU Lesser General Public License
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; along with the MPIR Library; see the file COPYING.LIB. If not, write
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; to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
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; Boston, MA 02110-1301, USA.
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; mp_limb_t mpn_lshift1(mp_ptr Op2, mp_srcptr Op1, mp_size_t Size1 )
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; Linux RAX RDI RSI RDX
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; Win7 RAX RCX RDX R8
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;
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; Description:
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; The function shifts Op1 left by one bit, stores the result in Op2 (non-
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; destructive shl) and hands back the shifted-out most significant bit of Op1.
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; The function operates decreasing in memory supporting in-place operation.
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;
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; Caveats:
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; - the AVX version uses mnemonics only available on Haswell, Broadwell and
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; Skylake cores
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; - the behaviour of cache prefetching in combination with AVX shifting seems
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; somewhat erratic
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; - slight (a few clock cycles) degradation for 1/2 LD1$ sizes
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; - slight (a few percent) improvement for full LD1$ sizes
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; - substantial (>10%) improvement for 1/2 LD2$ sizes
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; - slight (a few percent) improvement for full LD2$ sizes
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; - slight (a few percent) degradation for 1/2 LD3$ sizes
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; - substantial (around 10%) degradation for full LD3$ sizes
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;
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; Comments:
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; - implemented, tested and benched on 21.02.2016 by jn
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; - includes cache prefetching
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%define USE_WIN64
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%include 'yasm_mac.inc'
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BITS 64
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%ifdef USE_WIN64
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%define Op2 RCX
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%define Op1 RDX
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%define Size1 R8
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%define Limb1 R9
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%define Limb2 R10
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%define Offs -512 ; used direct def. to stay in Win scratch regs
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%define ShlDL0 XMM2 ; ATTN: this must match ShlQL0 definition
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%define ShrDL0 XMM3 ; ATTN: this must match ShrQL0 definition
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%define QLimb0 YMM0
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%define QLimb1 YMM1
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%define ShlQL0 YMM2
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%define ShrQL0 YMM3
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%define ShlQL1 YMM4
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%define ShrQL1 YMM5
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%else
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%define Op2 RDI
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%define Op1 RSI
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%define Size1 RDX
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%define Limb1 R8
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%define Limb2 R9
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%define Offs -512 ; used direct def. to stay in Win scratch regs
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%define ShlDL0 XMM2 ; ATTN: this must match ShlQL0 definition
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%define ShrDL0 XMM3 ; ATTN: this must match ShrQL0 definition
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%define QLimb0 YMM0
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%define QLimb1 YMM1
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%define ShlQL0 YMM2
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%define ShrQL0 YMM3
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%define ShlQL1 YMM4
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%define ShrQL1 YMM5
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%endif
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align 32
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LEAF_PROC mpn_lshift1
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xor EAX, EAX
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sub Size1, 1
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jc .Exit ;ajs:notshortform ; Size1=0 =>
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lea Op1, [Op1+8*Size1]
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lea Op2, [Op2+8*Size1]
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mov Limb1, [Op1]
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shld RAX, Limb1, 1
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or Size1, Size1
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je .lShl1EquPost ;ajs:notshortform ; Size1=1 =>
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cmp Size1, 8
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jc .lShl1EquFour ;ajs:notshortform ; AVX inefficient =>
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; first align Op2 to 32 bytes
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test Op2, 8
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jne .lShl1EquA16
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mov Limb2, [Op1-8]
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shld Limb1, Limb2, 1
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mov [Op2], Limb1
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mov Limb1, Limb2
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sub Op1, 8
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sub Op2, 8
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sub Size1, 1
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.lShl1EquA16:
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test Op2, 16
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jne .lShl1EquAVX
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mov Limb2, [Op1-8]
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shld Limb1, Limb2, 1
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mov [Op2], Limb1
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mov Limb1, [Op1-16]
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shld Limb2, Limb1, 1
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mov [Op2-8], Limb2
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sub Op1, 16
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sub Op2, 16
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sub Size1, 2
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.lShl1EquAVX:
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; pre-fetch first quad-limb
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vmovdqu QLimb0, [Op1-24]
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vpsrlq ShrQL0, QLimb0, 63
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vpermq ShrQL0, ShrQL0, 147 ; 0b10010011
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sub Op1, 32
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sub Size1, 4
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jmp .lShl1EquAVXCheck
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; main loop requires on entry:
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; - 0.60 cycles per limb in LD1$
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; - 0.60-0.75 cycles per limb in LD2$
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; - 0.75-1.00 cycles per limb in LD3$
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align 16
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.lShl1EquAVXLoop:
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%ifdef USE_PREFETCH
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prefetchnta [Op1+Offs]
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%endif
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vmovdqu QLimb1, [Op1-24]
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vpsllq ShlQL0, QLimb0, 1
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vmovdqu QLimb0, [Op1-56]
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vpsrlq ShrQL1, QLimb1, 63
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vpermq ShrQL1, ShrQL1, 147 ; 0b10010011
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vpblendd ShrQL0, ShrQL0, ShrQL1, 3 ; 0b00000011
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vpor ShlQL0, ShlQL0, ShrQL0
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vpsllq ShlQL1, QLimb1, 1
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vpsrlq ShrQL0, QLimb0, 63
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vpermq ShrQL0, ShrQL0, 147 ; 0b10010011
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vpblendd ShrQL1, ShrQL1, ShrQL0, 3 ; 0b00000011
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vmovdqa [Op2-24], ShlQL0
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vpor ShlQL1, ShlQL1, ShrQL1
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vmovdqa [Op2-56], ShlQL1
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sub Op1, 64
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sub Op2, 64
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.lShl1EquAVXCheck:
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sub Size1, 8
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jnc .lShl1EquAVXLoop
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mov Limb2, [Op1]
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mov Limb1, Limb2
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shr Limb2, 63
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%if 1
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vmovq ShlDL0, Limb2
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vpblendd ShrQL0, ShrQL0, ShlQL0, 3
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%else
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; I am mixing in a single SSE4.1 instruction into otherwise pure AVX2
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; this is generating stalls on Haswell & Broadwell architecture (Agner Fog)
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; but it is only executed once and there is no AVX2 based alternative
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; Insert value of Limb2 into the 0-th qword of ShrDL0
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pinsrq ShrDL0, Limb2, 0 ; SSE4.1
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%endif
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vpsllq ShlQL0, QLimb0, 1
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vpor ShlQL0, ShlQL0, ShrQL0
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vmovdqa [Op2-24], ShlQL0
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sub Op2, 32
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add Size1, 8
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; shift remaining max. 7 limbs with SHLD mnemonic
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.lShl1EquFour:
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sub Op1, 8
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test Size1, 4
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je .lShl1EquTwo
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mov Limb2, [Op1]
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shld Limb1, Limb2, 1
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mov [Op2], Limb1
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mov Limb1, [Op1-8]
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shld Limb2, Limb1, 1
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mov [Op2-8], Limb2
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mov Limb2, [Op1-16]
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shld Limb1, Limb2, 1
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mov [Op2-16], Limb1
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mov Limb1, [Op1-24]
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shld Limb2, Limb1, 1
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mov [Op2-24], Limb2
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sub Op1, 32
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sub Op2, 32
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.lShl1EquTwo:
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test Size1, 2
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je .lShl1EquOne
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mov Limb2, [Op1]
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shld Limb1, Limb2, 1
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mov [Op2], Limb1
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mov Limb1, [Op1-8]
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shld Limb2, Limb1, 1
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mov [Op2-8], Limb2
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sub Op1, 16
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sub Op2, 16
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.lShl1EquOne:
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test Size1, 1
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je .lShl1EquPost
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mov Limb2, [Op1]
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shld Limb1, Limb2, 1
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mov [Op2], Limb1
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mov Limb1, Limb2
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sub Op2, 8
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.lShl1EquPost:
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shl Limb1, 1
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mov [Op2], Limb1
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.Exit:
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vzeroupper
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ret
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.end:
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