184 lines
5.1 KiB
ActionScript
184 lines
5.1 KiB
ActionScript
; **************************************************************************
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; x86_64 mpn_add_n -- Add two limb vectors of the same length > 0 and store
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; sum in a third limb vector.
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;
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; Copyright (C) 2006 Jason Worth Martin <jason.worth.martin@gmail.com>
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;
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; This program is free software; you can redistribute it and/or modify
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; it under the terms of the GNU Lesser General Public License as published
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; by the Free Software Foundation; either version 2 of the License, or
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; (at your option) any later version.
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;
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; This program is distributed in the hope that it will be useful,
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; but WITHOUT ANY WARRANTY; without even the implied warranty of
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; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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; GNU General Public License for more details.
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;
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; You should have received a copy of the GNU Lesser General Public License
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; along with this program; if not, write to the Free Software Foundation,
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; Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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;
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; **************************************************************************
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;
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;
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; CREDITS
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;
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; This code is based largely on Pierrick Gaudry's excellent assembly
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; support for the AMD64 architecture. (Note that Intel64 and AMD64,
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; while using the same instruction set, have very different
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; microarchitectures. So, this code performs very poorly on AMD64
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; machines even though it is near-optimal on Intel64.)
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;
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; Roger Golliver works for Intel and provided insightful improvements
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; particularly in using the "lea" instruction to perform additions
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; and register-to-register moves.
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;
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; Eric Bainville has a brilliant exposition of optimizing arithmetic for
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; AMD64 (http://www.bealto.it). I adapted many of the ideas he
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; describes to Intel64.
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;
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; Agner Fog is a demigod in the x86 world. If you are reading assembly
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; code files and you haven't heard of Agner Fog, then take a minute to
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; look over his software optimization manuals (http://www.agner.org/).
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; They are superb.
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;
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; *********************************************************************
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%include 'yasm_mac.inc'
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;
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; If YASM supports lahf and sahf instructions, then we'll get rid
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; of this.
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;
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%define save_CF_to_reg_a db 0x9f
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%define get_CF_from_reg_a db 0x9e
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; cycles/limb
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; Hammer: 2.5 (for 1024 limbs)
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; Woodcrest: 2.6 (for 1024 limbs)
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; INPUT PARAMETERS
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; rp rdi
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; up rsi
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; vp rdx
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; n rcx
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BITS 64
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GLOBAL_FUNC mpn_add_n
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push rbp ; Save off callee-save registers
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push rbx
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push r12
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push r13
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push r14
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push r15
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xor r15,r15 ; r15 will be our index, so
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; I'll call it i here after
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save_CF_to_reg_a ; Save CF
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mov r9,rcx
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sub r9,4 ; r9 = n-(i+4)
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align 16 ; aligning for loop
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L_mpn_add_n_main_loop:
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; The goal of our main unrolled loop is to keep all the
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; execution units as busy as possible. Since
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; there are three ALUs, we try to perform three
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; adds at a time. Of course, we will have the
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; carry dependency, so there is at least one
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; clock cycle between each adc. However, we'll
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; try to keep the other execution units busy
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; with loads and stores at the same time so that
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; our net throughput is close to one add per clock
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; cycle. Hopefully this function will have asymptotic
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; behavior of taking 3*n clock cycles where n is the
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; number of limbs to add.
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;
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; Note that I'm using FOUR adds at a time, this is just
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; because I wanted to use up all available registers since
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; I'm hoping the out-of-order and loop-pipeline logic in
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; the Xeon will help us out.
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; See if we are still looping
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jle L_mpn_add_n_loop_done
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get_CF_from_reg_a ; recover CF
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; Load inputs into rbx and r8
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; add with carry, and put result in r8
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; then store r8 to output.
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mov rbx,[rsi+r15*8]
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mov r8,[rdx+r15*8]
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adc r8,rbx
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mov [rdi+r15*8],r8
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; Load inputs into r9 and r10
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; add with carry, and put result in r10
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; then store r10 to output.
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mov r9,[8+rsi+r15*8]
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mov r10,[8+rdx+r15*8]
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adc r10,r9
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mov [8+rdi+r15*8],r10
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; Load inputs into r11 and r12
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; add with carry, and put result in r12
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; then store r12 to output.
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mov r11,[16+rsi+r15*8]
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mov r12,[16+rdx+r15*8]
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adc r12,r11
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mov [16+rdi+r15*8],r12
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; Load inputs into r13 and r14
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; add with carry, and put result in r14
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; then store r14 to output.
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mov r13,[24+rsi+r15*8]
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mov r14,[24+rdx+r15*8]
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adc r14,r13
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mov [24+rdi+r15*8],r14
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save_CF_to_reg_a ; save CF
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mov r10,r15
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add r10,8
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add r15,4 ; increment by 4.
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mov r9,rcx
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sub r9,r10 ; r9 = n-(i+4)
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jmp L_mpn_add_n_main_loop
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L_mpn_add_n_loop_done:
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mov r15,rcx ;
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sub r15,r9 ; r15 = n-(n-(i+4))=i+4
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sub r15,4 ; r15 = i
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cmp r15,rcx
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L_mpn_add_n_post_loop:
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je L_mpn_add_n_exit
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get_CF_from_reg_a ; recover CF
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; Load inputs into rbx and r8
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; add with carry, and put result in r8
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; then store r8 to output.
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mov rbx,[rsi+r15*8]
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mov r8,[rdx+r15*8]
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adc r8,rbx
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mov [rdi+r15*8],r8
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save_CF_to_reg_a ; save CF
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add r15,1
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cmp r15,rcx
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jmp L_mpn_add_n_post_loop
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L_mpn_add_n_exit:
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xor rcx,rcx
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get_CF_from_reg_a ; recover the CF
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mov rax,rcx ; Clears rax without affecting carry flag
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adc rax,rax ; returns carry status.
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pop r15 ; restore callee-save registers
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pop r14
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pop r13
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pop r12
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pop rbx
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pop rbp
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ret
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