a197a2d3eb
Removed directories for no longer supported architectures.
38 lines
1.5 KiB
NASM
38 lines
1.5 KiB
NASM
dnl Intel P6 mpn_divexact_by3 -- mpn division by 3, expecting no remainder.
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dnl Copyright 2000, 2002 Free Software Foundation, Inc.
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dnl
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dnl This file is part of the GNU MP Library.
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dnl
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dnl The GNU MP Library is free software; you can redistribute it and/or
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dnl modify it under the terms of the GNU Lesser General Public License as
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dnl published by the Free Software Foundation; either version 2.1 of the
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dnl License, or (at your option) any later version.
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dnl
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dnl The GNU MP Library is distributed in the hope that it will be useful,
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dnl but WITHOUT ANY WARRANTY; without even the implied warranty of
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dnl MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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dnl Lesser General Public License for more details.
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dnl
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dnl You should have received a copy of the GNU Lesser General Public
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dnl License along with the GNU MP Library; see the file COPYING.LIB. If
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dnl not, write to the Free Software Foundation, Inc., 51 Franklin Street,
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dnl Fifth Floor, Boston, MA 02110-1301, USA.
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include(`../config.m4')
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C P6: 8.5 cycles/limb
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C The P5 code runs well on P6, in fact better than anything else found so
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C far. An imul is 4 cycles, meaning the two cmp/sbbl pairs on the dependent
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C path are taking 4.5 cycles.
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C
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C The destination cache line prefetching is unnecessary on P6, but removing
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C it is a 2 cycle slowdown (approx), so it must be inducing something good
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C in the out of order execution.
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MULFUNC_PROLOGUE(mpn_divexact_by3c)
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include_mpn(`x86/pentium/diveby3.asm')
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