9bf78f0866
2. Remove the now redundant 32 to 64 register mapping for mp_size_t inputs in Windows assembler
214 lines
4.6 KiB
NASM
214 lines
4.6 KiB
NASM
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; Copyright 2008 Jason Moxham
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;
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; Windows Conversion Copyright 2008 Brian Gladman
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;
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; This file is part of the MPIR Library.
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; The MPIR Library is free software; you can redistribute it and/or modify
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; it under the terms of the GNU Lesser General Public License as published
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; by the Free Software Foundation; either version 2.1 of the License, or (at
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; your option) any later version.
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; The MPIR Library is distributed in the hope that it will be useful, but
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; WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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; License for more details.
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; You should have received a copy of the GNU Lesser General Public License
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; along with the MPIR Library; see the file COPYING.LIB. If not, write
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; to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
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; Boston, MA 02110-1301, USA.
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;
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; mp_limb_t mpn_addmul_2(mp_ptr, mp_ptr, mp_size_t, mp_ptr)
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; rax rdi rsi rdx rcx
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; rax rcx rdx r8 r9
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%include "yasm_mac.inc"
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CPU Athlon64
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BITS 64
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%define reg_save_list rbx, rsi, rdi, r12
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FRAME_PROC mpn_addmul_2, 0, reg_save_list
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mov rdi, rcx
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mov rsi, rdx
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mov rax, r8
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mov rcx, [r9]
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mov r8, [r9+8]
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mov rbx, 4
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sub rbx, rax
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lea rsi, [rsi+rax*8-32]
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lea rdi, [rdi+rax*8-32]
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mov r10, 0
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mov rax, [rsi+rbx*8]
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mul rcx
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mov r12, rax
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mov r9, rdx
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cmp rbx, 0
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jge .2
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xalign 16
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.1:
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mov rax, [rsi+rbx*8]
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mul r8
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add r9, rax
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mov rax, [rsi+rbx*8+8]
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adc r10, rdx
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mov r11, 0
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mul rcx
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add [rdi+rbx*8], r12
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adc r9, rax
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mov r12, 0
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adc r10, rdx
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mov rax, [rsi+rbx*8+8]
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adc r11, 0
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mul r8
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add [rdi+rbx*8+8], r9
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adc r10, rax
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adc r11, rdx
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mov rax, [rsi+rbx*8+16]
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mul rcx
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add r10, rax
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mov rax, [rsi+rbx*8+16]
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adc r11, rdx
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adc r12, 0
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mul r8
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add [rdi+rbx*8+16], r10
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mov r9, 0
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adc r11, rax
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mov r10, 0
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mov rax, [rsi+rbx*8+24]
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adc r12, rdx
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mov r15, r15
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mul rcx
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add r11, rax
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mov rax, [rsi+rbx*8+24]
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adc r12, rdx
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adc r9, 0
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mul r8
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add [rdi+rbx*8+24], r11
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adc r12, rax
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adc r9, rdx
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mov rax, [rsi+rbx*8+32]
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mul rcx
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add r12, rax
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adc r9, rdx
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adc r10, 0
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add rbx, 4
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jnc .1
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.2:
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mov rax, [rsi+rbx*8]
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mul r8
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cmp rbx, 2
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ja .6
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jz .5
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jp .4
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.3:
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add r9, rax
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mov rax, [rsi+rbx*8+8]
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adc r10, rdx
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mov r11, 0
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mul rcx
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add [rdi+rbx*8], r12
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adc r9, rax
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mov r12, 0
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adc r10, rdx
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mov rax, [rsi+rbx*8+8]
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adc r11, 0
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mul r8
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add [rdi+rbx*8+8], r9
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adc r10, rax
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adc r11, rdx
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mov rax, [rsi+rbx*8+16]
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mul rcx
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add r10, rax
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mov rax, [rsi+rbx*8+16]
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adc r11, rdx
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adc r12, 0
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mul r8
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add [rdi+rbx*8+16], r10
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mov r9, 0
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adc r11, rax
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; padding
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mov r10, 0
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mov rax, [rsi+rbx*8+24]
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adc r12, rdx
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; padding
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mov r15, r15
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mul rcx
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add r11, rax
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mov rax, [rsi+rbx*8+24]
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adc r12, rdx
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adc r9, 0
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mul r8
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add [rdi+rbx*8+24], r11
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adc r12, rax
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adc r9, rdx
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mov [rdi+rbx*8+32], r12
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mov rax, r9
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jmp .7
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xalign 16
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.4:
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add r9, rax
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mov rax, [rsi+rbx*8+8]
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adc r10, rdx
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mov r11, 0
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mul rcx
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add [rdi+rbx*8], r12
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adc r9, rax
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mov r12, 0
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adc r10, rdx
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mov rax, [rsi+rbx*8+8]
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adc r11, 0
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mul r8
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add [rdi+rbx*8+8], r9
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adc r10, rax
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adc r11, rdx
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mov rax, [rsi+rbx*8+16]
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mul rcx
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add r10, rax
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mov rax, [rsi+rbx*8+16]
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adc r11, rdx
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adc r12, 0
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mul r8
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add [rdi+rbx*8+16], r10
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adc r11, rax
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adc r12, rdx
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mov [rdi+rbx*8+24], r11
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mov rax, r12
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jmp .7
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xalign 16
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.5:
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add r9, rax
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mov rax, [rsi+rbx*8+8]
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adc r10, rdx
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mov r11, 0
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mul rcx
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add [rdi+rbx*8], r12
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adc r9, rax
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mov r12, 0
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adc r10, rdx
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mov rax, [rsi+rbx*8+8]
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adc r11, 0
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mul r8
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add [rdi+rbx*8+8], r9
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adc r10, rax
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adc r11, rdx
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mov [rdi+rbx*8+16], r10
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mov rax, r11
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jmp .7
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xalign 16
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.6:
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add [rdi+rbx*8], r12
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adc r9, rax
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adc r10, rdx
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mov [rdi+rbx*8+8], r9
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mov rax, r10
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.7:
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END_PROC reg_save_list
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end
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