201 lines
7.6 KiB
Plaintext
201 lines
7.6 KiB
Plaintext
Copyright 1996, 1997, 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software
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Foundation, Inc.
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This file is part of the GNU MP Library.
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The GNU MP Library is free software; you can redistribute it and/or modify it
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under the terms of the GNU Lesser General Public License as published by the
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Free Software Foundation; either version 2.1 of the License, or (at your
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option) any later version.
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The GNU MP Library is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License
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for more details.
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You should have received a copy of the GNU Lesser General Public License along
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with the GNU MP Library; see the file COPYING.LIB. If not, write to the Free
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Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
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USA.
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This directory contains mpn functions optimized for DEC Alpha processors.
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ALPHA ASSEMBLY RULES AND REGULATIONS
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The `.prologue N' pseudo op marks the end of instruction that needs special
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handling by unwinding. It also says whether $27 is really needed for computing
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the gp. The `.mask M' pseudo op says which registers are saved on the stack,
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and at what offset in the frame.
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Cray T3 code is very very different...
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"$6" / "$f6" etc is the usual syntax for registers, but on Unicos instead "r6"
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/ "f6" is required. We use the "r6" / "f6" forms, and have m4 defines expand
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them to "$6" or "$f6" where necessary.
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"0x" introduces a hex constant in gas and DEC as, but on Unicos "^X" is
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required. The X() macro accomodates this difference.
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"cvttqc" is required by DEC as, "cvttq/c" is required by Unicos, and gas will
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accept either. We use cvttqc and have an m4 define expand to cvttq/c where
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necessary.
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"not" as an alias for "ornot r31, ..." is available in gas and DEC as, but not
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the Unicos assembler. The full "ornot" must be used.
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"unop" is not available in Unicos. We make an m4 define to the usual "ldq_u
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r31,0(r30)", and in fact use that define on all systems since it comes out the
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same.
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"!literal!123" etc explicit relocations as per Tru64 4.0 are apparently not
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available in older alpha assemblers (including gas prior to 2.12), according to
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the GCC manual, so the assembler macro forms must be used (eg. ldgp).
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RELEVANT OPTIMIZATION ISSUES
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EV4
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1. This chip has very limited store bandwidth. The on-chip L1 cache is write-
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through, and a cache line is transfered from the store buffer to the off-
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chip L2 in as much 15 cycles on most systems. This delay hurts mpn_add_n,
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mpn_sub_n, mpn_lshift, and mpn_rshift.
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2. Pairing is possible between memory instructions and integer arithmetic
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instructions.
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3. mulq and umulh are documented to have a latency of 23 cycles, but 2 of these
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cycles are pipelined. Thus, multiply instructions can be issued at a rate
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of one each 21st cycle.
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EV5
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1. The memory bandwidth of this chip is good, both for loads and stores. The
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L1 cache can handle two loads or one store per cycle, but two cycles after a
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store, no ld can issue.
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2. mulq has a latency of 12 cycles and an issue rate of 1 each 8th cycle.
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umulh has a latency of 14 cycles and an issue rate of 1 each 10th cycle.
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(Note that published documentation gets these numbers slightly wrong.)
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3. mpn_add_n. With 4-fold unrolling, we need 37 instructions, whereof 12
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are memory operations. This will take at least
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ceil(37/2) [dual issue] + 1 [taken branch] = 19 cycles
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We have 12 memory cycles, plus 4 after-store conflict cycles, or 16 data
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cache cycles, which should be completely hidden in the 19 issue cycles.
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The computation is inherently serial, with these dependencies:
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ldq ldq
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\ /\
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(or) addq |
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|\ / \ |
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| addq cmpult
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\ | |
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cmpult |
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\ /
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or
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I.e., 3 operations are needed between carry-in and carry-out, making 12
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cycles the absolute minimum for the 4 limbs. We could replace the `or' with
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a cmoveq/cmovne, which could issue one cycle earlier that the `or', but that
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might waste a cycle on EV4. The total depth remain unaffected, since cmov
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has a latency of 2 cycles.
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addq
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/ \
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addq cmpult
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| \
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cmpult -> cmovne
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Montgomery has a slightly different way of computing carry that requires one
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less instruction, but has depth 4 (instead of the current 3). Since the code
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is currently instruction issue bound, Montgomery's idea should save us 1/2
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cycle per limb, or bring us down to a total of 17 cycles or 4.25 cycles/limb.
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Unfortunately, this method will not be good for the EV6.
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4. addmul_1 and friends: We previously had a scheme for splitting the single-
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limb operand in 21-bits chunks and the multi-limb operand in 32-bit chunks,
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and then use FP operations for every 2nd multiply, and integer operations
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for every 2nd multiply.
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But it seems much better to split the single-limb operand in 16-bit chunks,
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since we save many integer shifts and adds that way. See powerpc64/README
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for some more details.
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EV6
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Here we have a really parallel pipeline, capable of issuing up to 4 integer
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instructions per cycle. In actual practice, it is never possible to sustain
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more than 3.5 integer insns/cycle due to rename register shortage. One integer
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multiply instruction can issue each cycle. To get optimal speed, we need to
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pretend we are vectorizing the code, i.e., minimize the depth of recurrences.
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There are two dependencies to watch out for. 1) Address arithmetic
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dependencies, and 2) carry propagation dependencies.
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We can avoid serializing due to address arithmetic by unrolling loops, so that
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addresses don't depend heavily on an index variable. Avoiding serializing
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because of carry propagation is trickier; the ultimate performance of the code
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will be determined of the number of latency cycles it takes from accepting
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carry-in to a vector point until we can generate carry-out.
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Most integer instructions can execute in either the L0, U0, L1, or U1
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pipelines. Shifts only execute in U0 and U1, and multiply only in U1.
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CMOV instructions split into two internal instructions, CMOV1 and CMOV2. CMOV
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split the mapping process (see pg 2-26 in cmpwrgd.pdf), suggesting the CMOV
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should always be placed as the last instruction of an aligned 4 instruction
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block, or perhaps simply avoided.
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Perhaps the most important issue is the latency between the L0/U0 and L1/U1
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clusters; a result obtained on either cluster has an extra cycle of latency for
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consumers in the opposite cluster. Because of the dynamic nature of the
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implementation, it is hard to predict where an instruction will execute.
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REFERENCES
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"Alpha Architecture Handbook", version 4, Compaq, October 1998, order number
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EC-QD2KC-TE.
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"Alpha 21164 Microprocessor Hardware Reference Manual", Compaq, December 1998,
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order number EC-QP99C-TE.
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"Alpha 21264/EV67 Microprocessor Hardware Reference Manual", revision 1.4,
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Compaq, September 2000, order number DS-0028B-TE.
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"Compiler Writer's Guide for the Alpha 21264", Compaq, June 1999, order number
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EC-RJ66A-TE.
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All of the above are available online from
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http://ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html
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ftp://ftp.compaq.com/pub/products/alphaCPUdocs
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"Tru64 Unix Assembly Language Programmer's Guide", Compaq, March 1996, part
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number AA-PS31D-TE.
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"Digital UNIX Calling Standard for Alpha Systems", Digital Equipment Corp,
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March 1996, part number AA-PY8AC-TE.
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The above are available online,
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http://h30097.www3.hp.com/docs/pub_page/V40F_DOCS.HTM
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(Dunno what h30097 means in this URL, but if it moves try searching for "tru64
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online documentation" from the main www.hp.com page.)
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----------------
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Local variables:
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mode: text
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fill-column: 79
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End:
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