237 lines
4.7 KiB
NASM
237 lines
4.7 KiB
NASM
dnl Alpha mpn_addlsh1_n/mpn_sublsh1_n -- rp[] = up[] +- (vp[] << 1).
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dnl Copyright 2003 Free Software Foundation, Inc.
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dnl This file is part of the GNU MP Library.
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dnl The GNU MP Library is free software; you can redistribute it and/or modify
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dnl it under the terms of the GNU Lesser General Public License as published
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dnl by the Free Software Foundation; either version 2.1 of the License, or (at
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dnl your option) any later version.
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dnl The GNU MP Library is distributed in the hope that it will be useful, but
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dnl WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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dnl or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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dnl License for more details.
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dnl You should have received a copy of the GNU Lesser General Public License
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dnl along with the GNU MP Library; see the file COPYING.LIB. If not, write
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dnl to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
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dnl Boston, MA 02110-1301, USA.
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include(`../config.m4')
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C cycles/limb
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C EV4: 12.5
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C EV5: 6.25
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C EV6: 4.375 (i.e., worse than separate mpn_lshift and mpn_add_n at 3.875)
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C TODO
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C * Write special version for ev6, as this is a slowdown for 100 < n < 2200
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C compared to separate mpn_lshift and mpn_add_n.
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C * Use addq instead of sll for left shift, and similarly cmplt instead of srl
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C for right shift.
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dnl INPUT PARAMETERS
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define(`rp',`r16')
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define(`up',`r17')
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define(`vp',`r18')
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define(`n', `r19')
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define(`u0', `r8')
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define(`u1', `r1')
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define(`u2', `r2')
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define(`u3', `r3')
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define(`v0', `r4')
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define(`v1', `r5')
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define(`v2', `r6')
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define(`v3', `r7')
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define(`cy0', `r0')
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define(`cy1', `r20')
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define(`cy', `r22')
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define(`rr', `r24')
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define(`ps', `r25')
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define(`sl', `r28')
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define(OPERATION_addlsh1_n,1)
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ifdef(`OPERATION_addlsh1_n',`
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define(ADDSUB, addq)
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define(CARRY, `cmpult $1,$2,$3')
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define(func, mpn_addlsh1_n)
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')
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ifdef(`OPERATION_sublsh1_n',`
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define(ADDSUB, subq)
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define(CARRY, `cmpult $2,$1,$3')
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define(func, mpn_sublsh1_n)
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')
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ASM_START()
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PROLOGUE(func)
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lda n, -4(n)
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bis r31, r31, cy1
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and n, 3, r1
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beq r1, $Lb00
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cmpeq r1, 1, r2
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bne r2, $Lb01
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cmpeq r1, 2, r2
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bne r2, $Lb10
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$Lb11: C n = 3, 7, 11, ...
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ldq v0, 0(vp)
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ldq u0, 0(up)
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ldq v1, 8(vp)
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ldq u1, 8(up)
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ldq v2, 16(vp)
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ldq u2, 16(up)
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lda vp, 24(vp)
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lda up, 24(up)
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bge n, $Loop
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br r31, $Lcj3
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$Lb10: C n = 2, 6, 10, ...
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bis r31, r31, cy0
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ldq v1, 0(vp)
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ldq u1, 0(up)
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ldq v2, 8(vp)
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ldq u2, 8(up)
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lda rp, -8(rp)
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blt n, $Lcj2
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ldq v3, 16(vp)
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ldq u3, 16(up)
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lda vp, 48(vp)
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lda up, 16(up)
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br r31, $LL10
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$Lb01: C n = 1, 5, 9, ...
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ldq v2, 0(vp)
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ldq u2, 0(up)
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lda rp, -16(rp)
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blt n, $Lcj1
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ldq v3, 8(vp)
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ldq u3, 8(up)
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ldq v0, 16(vp)
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ldq u0, 16(up)
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lda vp, 40(vp)
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lda up, 8(up)
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lda rp, 32(rp)
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br r31, $LL01
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$Lb00: C n = 4, 8, 12, ...
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bis r31, r31, cy0
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ldq v3, 0(vp)
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ldq u3, 0(up)
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ldq v0, 8(vp)
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ldq u0, 8(up)
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ldq v1, 16(vp)
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ldq u1, 16(up)
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lda vp, 32(vp)
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lda rp, 8(rp)
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br r31, $LL00x
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ALIGN(16)
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C 0
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$Loop: sll v0, 1, sl C left shift vlimb
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ldq v3, 0(vp)
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C 1
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ADDSUB u0, sl, ps C ulimb + (vlimb << 1)
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ldq u3, 0(up)
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C 2
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ADDSUB ps, cy1, rr C consume carry from previous operation
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srl v0, 63, cy0 C carry out #1
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C 3
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CARRY( ps, u0, cy) C carry out #2
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stq rr, 0(rp)
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C 4
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addq cy, cy0, cy0 C combine carry out #1 and #2
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CARRY( rr, ps, cy) C carry out #3
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C 5
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addq cy, cy0, cy0 C final carry out
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lda vp, 32(vp) C bookkeeping
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C 6
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$LL10: sll v1, 1, sl
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ldq v0, -24(vp)
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C 7
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ADDSUB u1, sl, ps
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ldq u0, 8(up)
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C 8
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ADDSUB ps, cy0, rr
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srl v1, 63, cy1
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C 9
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CARRY( ps, u1, cy)
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stq rr, 8(rp)
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C 10
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addq cy, cy1, cy1
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CARRY( rr, ps, cy)
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C 11
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addq cy, cy1, cy1
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lda rp, 32(rp) C bookkeeping
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C 12
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$LL01: sll v2, 1, sl
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ldq v1, -16(vp)
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C 13
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ADDSUB u2, sl, ps
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ldq u1, 16(up)
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C 14
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ADDSUB ps, cy1, rr
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srl v2, 63, cy0
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C 15
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CARRY( ps, u2, cy)
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stq rr, -16(rp)
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C 16
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addq cy, cy0, cy0
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CARRY( rr, ps, cy)
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C 17
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addq cy, cy0, cy0
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$LL00x: lda up, 32(up) C bookkeeping
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C 18
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sll v3, 1, sl
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ldq v2, -8(vp)
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C 19
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ADDSUB u3, sl, ps
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ldq u2, -8(up)
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C 20
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ADDSUB ps, cy0, rr
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srl v3, 63, cy1
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C 21
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CARRY( ps, u3, cy)
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stq rr, -8(rp)
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C 22
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addq cy, cy1, cy1
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CARRY( rr, ps, cy)
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C 23
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addq cy, cy1, cy1
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lda n, -4(n) C bookkeeping
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C 24
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bge n, $Loop
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$Lcj3: sll v0, 1, sl
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ADDSUB u0, sl, ps
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ADDSUB ps, cy1, rr
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srl v0, 63, cy0
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CARRY( ps, u0, cy)
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stq rr, 0(rp)
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addq cy, cy0, cy0
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CARRY( rr, ps, cy)
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addq cy, cy0, cy0
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$Lcj2: sll v1, 1, sl
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ADDSUB u1, sl, ps
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ADDSUB ps, cy0, rr
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srl v1, 63, cy1
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CARRY( ps, u1, cy)
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stq rr, 8(rp)
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addq cy, cy1, cy1
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CARRY( rr, ps, cy)
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addq cy, cy1, cy1
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$Lcj1: sll v2, 1, sl
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ADDSUB u2, sl, ps
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ADDSUB ps, cy1, rr
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srl v2, 63, cy0
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CARRY( ps, u2, cy)
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stq rr, 16(rp)
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addq cy, cy0, cy0
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CARRY( rr, ps, cy)
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addq cy, cy0, cy0
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ret r31,(r26),1
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EPILOGUE()
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ASM_END()
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