2051 lines
120 KiB
C
2051 lines
120 KiB
C
/* Generated by gen_x86_insn.py r2199, do not edit */
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static const x86_info_operand insn_operands[] = {
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None},
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{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
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{OPT_Mem, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
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{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
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{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
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{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
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{OPT_SIMDRM, OPS_256, 1, 0, OPTM_None, OPA_EA, OPAP_None},
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{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
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{OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
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{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
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{OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
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{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
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{OPT_Mem, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None},
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{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
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{OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
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{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEXImmSrc, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEXImmSrc, OPAP_None},
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{OPT_Mem, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEXImmSrc, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
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{OPT_Mem, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
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{OPT_Mem, OPS_8, 1, 0, OPTM_None, OPA_EA, OPAP_None},
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{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
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{OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
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{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
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{OPT_Mem, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
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{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
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{OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
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{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
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{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
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{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
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{OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
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{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
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{OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEXImmSrc, OPAP_None},
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{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
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{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
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{OPT_SIMDRM, OPS_256, 1, 0, OPTM_None, OPA_EA, OPAP_None},
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{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_VEXImmSrc, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEXImmSrc, OPAP_None},
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{OPT_Mem, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEXImmSrc, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
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{OPT_Mem, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
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{OPT_RM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
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{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEXImmSrc, OPAP_None},
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{OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
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{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
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{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
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{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_VEXImmSrc, OPAP_None},
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{OPT_SIMDRM, OPS_256, 1, 0, OPTM_None, OPA_EA, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None},
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{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_EA, OPAP_None},
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{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEXImmSrc, OPAP_None},
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{OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEXImmSrc, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
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{OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
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{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
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{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_VEXImmSrc, OPAP_None},
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{OPT_SIMDRM, OPS_256, 1, 0, OPTM_None, OPA_EA, OPAP_None},
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{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
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{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
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{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_VEXImmSrc, OPAP_None},
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{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
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{OPT_SIMDRM, OPS_256, 1, 0, OPTM_None, OPA_EA, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None},
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{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None},
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{OPT_Mem, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
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{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
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{OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
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{OPT_RM, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None},
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{OPT_Imm, OPS_8, 0, 0, OPTM_None, OPA_SImm, OPAP_None},
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{OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
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{OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
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{OPT_Imm, OPS_8, 0, 0, OPTM_None, OPA_SImm, OPAP_None},
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{OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
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{OPT_RM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
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{OPT_Imm, OPS_8, 0, 0, OPTM_None, OPA_SImm, OPAP_None},
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{OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
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{OPT_RM, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None},
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{OPT_Imm, OPS_16, 1, 0, OPTM_None, OPA_SImm, OPAP_SImm8},
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{OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
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{OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
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{OPT_Imm, OPS_32, 1, 0, OPTM_None, OPA_SImm, OPAP_SImm8},
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{OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
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{OPT_RM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
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{OPT_Imm, OPS_32, 1, 0, OPTM_None, OPA_SImm, OPAP_SImm8},
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{OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
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{OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
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{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
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{OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
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{OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
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{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
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{OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
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{OPT_Mem, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None},
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{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None},
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{OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
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{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None},
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{OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
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{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None},
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{OPT_Mem, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None},
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{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None},
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{OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
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{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None},
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{OPT_Mem, OPS_8, 1, 0, OPTM_None, OPA_EA, OPAP_None},
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{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None},
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{OPT_Mem, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
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{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None},
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{OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
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{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
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{OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
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{OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
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{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
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{OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None},
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{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
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{OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
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{OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
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{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
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{OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None},
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{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
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{OPT_Mem, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
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{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
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{OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
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{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
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{OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
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{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
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{OPT_RM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
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{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
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{OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
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{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
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{OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
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{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
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{OPT_Mem, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
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{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
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{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
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{OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
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{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
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{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
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{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
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{OPT_SIMDRM, OPS_256, 1, 0, OPTM_None, OPA_EA, OPAP_None},
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{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
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{OPT_Mem, OPS_8, 1, 0, OPTM_None, OPA_EA, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
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{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
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{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
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{OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
|
|
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_XMM0, OPS_128, 0, 0, OPTM_None, OPA_None, OPAP_None},
|
|
{OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_SIMDRM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
|
|
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_Mem, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
|
|
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
|
|
{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
|
|
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None},
|
|
{OPT_RM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
|
|
{OPT_RM, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
|
|
{OPT_RM, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_Creg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None},
|
|
{OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
|
|
{OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_Creg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None},
|
|
{OPT_RM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
|
|
{OPT_RM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_Creg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None},
|
|
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
|
|
{OPT_RM, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
|
|
{OPT_RM, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_RM, OPS_16, 0, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
|
|
{OPT_RM, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
|
|
{OPT_RM, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
|
|
{OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_RM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_RM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_RM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_SpareEA, OPAP_None},
|
|
{OPT_Imm, OPS_8, 0, 0, OPTM_None, OPA_SImm, OPAP_None},
|
|
{OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_SpareEA, OPAP_None},
|
|
{OPT_Imm, OPS_8, 0, 0, OPTM_None, OPA_SImm, OPAP_None},
|
|
{OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_SpareEA, OPAP_None},
|
|
{OPT_Imm, OPS_8, 0, 0, OPTM_None, OPA_SImm, OPAP_None},
|
|
{OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_SpareEA, OPAP_None},
|
|
{OPT_Imm, OPS_16, 1, 0, OPTM_None, OPA_SImm, OPAP_SImm8},
|
|
{OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_SpareEA, OPAP_None},
|
|
{OPT_Imm, OPS_32, 1, 0, OPTM_None, OPA_SImm, OPAP_SImm8},
|
|
{OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_SpareEA, OPAP_None},
|
|
{OPT_Imm, OPS_32, 1, 0, OPTM_None, OPA_SImm, OPAP_SImm8},
|
|
{OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_Mem, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_RM, OPS_8, 1, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Reg, OPS_8, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_Reg, OPS_8, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_RM, OPS_8, 1, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_ST0, OPS_80, 0, 0, OPTM_None, OPA_None, OPAP_None},
|
|
{OPT_Reg, OPS_80, 0, 0, OPTM_None, OPA_Op1Add, OPAP_None},
|
|
{OPT_Reg, OPS_80, 0, 0, OPTM_None, OPA_Op1Add, OPAP_None},
|
|
{OPT_ST0, OPS_80, 0, 0, OPTM_None, OPA_None, OPAP_None},
|
|
{OPT_SIMDRM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_SIMDRM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_SIMDRM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_Mem, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_Mem, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_Areg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None},
|
|
{OPT_MemOffs, OPS_8, 1, 1, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Areg, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
|
|
{OPT_MemOffs, OPS_16, 1, 1, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
|
|
{OPT_MemOffs, OPS_32, 1, 1, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Areg, OPS_64, 0, 0, OPTM_None, OPA_None, OPAP_None},
|
|
{OPT_MemOffs, OPS_64, 1, 1, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_MemOffs, OPS_8, 1, 1, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Areg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None},
|
|
{OPT_MemOffs, OPS_16, 1, 1, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Areg, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
|
|
{OPT_MemOffs, OPS_32, 1, 1, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
|
|
{OPT_MemOffs, OPS_64, 1, 1, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Areg, OPS_64, 0, 0, OPTM_None, OPA_None, OPAP_None},
|
|
{OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Op0Add, OPAP_None},
|
|
{OPT_Imm, OPS_64, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
|
|
{OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_Mem, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_Mem, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Mem, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_Areg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None},
|
|
{OPT_MemOffs, OPS_8, 1, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Areg, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
|
|
{OPT_MemOffs, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
|
|
{OPT_MemOffs, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_MemOffs, OPS_8, 1, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Areg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None},
|
|
{OPT_MemOffs, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Areg, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
|
|
{OPT_MemOffs, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
|
|
{OPT_RM, OPS_8, 1, 0, OPTM_None, OPA_EA, OPAP_ShortMov},
|
|
{OPT_Areg, OPS_8, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_RM, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_ShortMov},
|
|
{OPT_Areg, OPS_16, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_ShortMov},
|
|
{OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_RM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_ShortMov},
|
|
{OPT_Areg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_Areg, OPS_8, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_RM, OPS_8, 1, 0, OPTM_None, OPA_EA, OPAP_ShortMov},
|
|
{OPT_Areg, OPS_16, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_RM, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_ShortMov},
|
|
{OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_ShortMov},
|
|
{OPT_Areg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_RM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_ShortMov},
|
|
{OPT_Mem, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_SegReg, OPS_16, 1, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_SegReg, OPS_16, 1, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_SegReg, OPS_16, 1, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_SegReg, OPS_16, 1, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_SegReg, OPS_16, 1, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_RM, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Reg, OPS_8, 0, 0, OPTM_None, OPA_Op0Add, OPAP_None},
|
|
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
|
|
{OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_Op0Add, OPAP_None},
|
|
{OPT_Imm, OPS_16, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
|
|
{OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Op0Add, OPAP_None},
|
|
{OPT_Imm, OPS_32, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
|
|
{OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Op0Add, OPAP_None},
|
|
{OPT_Imm, OPS_64, 0, 0, OPTM_None, OPA_Imm, OPAP_None},
|
|
{OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Op0Add, OPAP_None},
|
|
{OPT_Imm, OPS_64, 1, 0, OPTM_None, OPA_Imm, OPAP_SImm32Avail},
|
|
{OPT_RM, OPS_8, 1, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Imm, OPS_8, 0, 0, OPTM_None, OPA_Imm, OPAP_None},
|
|
{OPT_RM, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Imm, OPS_16, 0, 0, OPTM_None, OPA_Imm, OPAP_None},
|
|
{OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Imm, OPS_32, 0, 0, OPTM_None, OPA_Imm, OPAP_None},
|
|
{OPT_RM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Imm, OPS_32, 0, 0, OPTM_None, OPA_Imm, OPAP_None},
|
|
{OPT_RM, OPS_8, 0, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
|
|
{OPT_RM, OPS_16, 0, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Imm, OPS_16, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
|
|
{OPT_RM, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Imm, OPS_32, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
|
|
{OPT_RM, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Imm, OPS_32, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
|
|
{OPT_CR4, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_CRReg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_CRReg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_CR4, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_CRReg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_DRReg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_DRReg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_DRReg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_Mem, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_Mem, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_Mem, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Areg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None},
|
|
{OPT_RM, OPS_8, 0, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Areg, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
|
|
{OPT_RM, OPS_16, 0, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
|
|
{OPT_RM, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Areg, OPS_64, 0, 0, OPTM_None, OPA_None, OPAP_None},
|
|
{OPT_RM, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_Mem, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_SIMDRM, OPS_256, 1, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_Mem, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
|
|
{OPT_Areg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None},
|
|
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
|
|
{OPT_Areg, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
|
|
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
|
|
{OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
|
|
{OPT_Dreg, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
|
|
{OPT_Areg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None},
|
|
{OPT_Dreg, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
|
|
{OPT_Areg, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
|
|
{OPT_Dreg, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
|
|
{OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
|
|
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_EAVEX, OPAP_None},
|
|
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
|
|
{OPT_MemrAX, OPS_Any, 0, 0, OPTM_None, OPA_AdSizeEA, OPAP_None},
|
|
{OPT_Creg, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
|
|
{OPT_Areg, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
|
|
{OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_Op0Add, OPAP_None},
|
|
{OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_Op0Add, OPAP_None},
|
|
{OPT_Areg, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
|
|
{OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
|
|
{OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Op0Add, OPAP_None},
|
|
{OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Op0Add, OPAP_None},
|
|
{OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
|
|
{OPT_Areg, OPS_64, 0, 0, OPTM_None, OPA_None, OPAP_None},
|
|
{OPT_Areg, OPS_64, 0, 0, OPTM_None, OPA_Op0Add, OPAP_None},
|
|
{OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Op0Add, OPAP_None},
|
|
{OPT_Areg, OPS_64, 0, 0, OPTM_None, OPA_None, OPAP_None},
|
|
{OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_Mem, OPS_Any, 1, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_Mem, OPS_Any, 1, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_Mem, OPS_Any, 1, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_RM, OPS_8, 0, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_RM, OPS_16, 0, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_RM, OPS_8, 0, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_RM, OPS_8, 0, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Creg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None},
|
|
{OPT_RM, OPS_8, 0, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Imm1, OPS_8, 1, 0, OPTM_None, OPA_None, OPAP_None},
|
|
{OPT_RM, OPS_16, 0, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Creg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None},
|
|
{OPT_RM, OPS_16, 0, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Imm1, OPS_8, 1, 0, OPTM_None, OPA_None, OPAP_None},
|
|
{OPT_RM, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Creg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None},
|
|
{OPT_RM, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Imm1, OPS_8, 1, 0, OPTM_None, OPA_None, OPAP_None},
|
|
{OPT_RM, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Creg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None},
|
|
{OPT_RM, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Imm1, OPS_8, 1, 0, OPTM_None, OPA_None, OPAP_None},
|
|
{OPT_SegReg, OPS_16, 1, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_Mem, OPS_80, 1, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Areg, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
|
|
{OPT_Imm, OPS_16, 1, 0, OPTM_None, OPA_Imm, OPAP_SImm8},
|
|
{OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
|
|
{OPT_Imm, OPS_32, 1, 0, OPTM_None, OPA_Imm, OPAP_SImm8},
|
|
{OPT_Areg, OPS_64, 0, 0, OPTM_None, OPA_None, OPAP_None},
|
|
{OPT_Imm, OPS_32, 1, 0, OPTM_None, OPA_Imm, OPAP_SImm8},
|
|
{OPT_RM, OPS_16, 0, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Imm, OPS_8, 0, 0, OPTM_None, OPA_SImm, OPAP_None},
|
|
{OPT_RM, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Imm, OPS_16, 0, 0, OPTM_None, OPA_Imm, OPAP_SImm8},
|
|
{OPT_RM, OPS_16, 0, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Imm, OPS_16, 1, 0, OPTM_None, OPA_Imm, OPAP_SImm8},
|
|
{OPT_RM, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Imm, OPS_8, 0, 0, OPTM_None, OPA_SImm, OPAP_None},
|
|
{OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Imm, OPS_32, 0, 0, OPTM_None, OPA_Imm, OPAP_SImm8},
|
|
{OPT_RM, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Imm, OPS_32, 1, 0, OPTM_None, OPA_Imm, OPAP_SImm8},
|
|
{OPT_RM, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Imm, OPS_8, 0, 0, OPTM_None, OPA_SImm, OPAP_None},
|
|
{OPT_RM, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Imm, OPS_32, 1, 0, OPTM_None, OPA_Imm, OPAP_SImm8},
|
|
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_Mem, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Mem, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_Mem, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_Mem, OPS_256, 1, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_RM, OPS_8, 1, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_RM, OPS_16, 0, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_SIMDRM, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_SIMDRM, OPS_256, 0, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Imm, OPS_Any, 0, 0, OPTM_None, OPA_JmpRel, OPAP_None},
|
|
{OPT_Creg, OPS_16, 0, 0, OPTM_None, OPA_AdSizeR, OPAP_None},
|
|
{OPT_Imm, OPS_Any, 0, 0, OPTM_None, OPA_JmpRel, OPAP_None},
|
|
{OPT_Creg, OPS_32, 0, 0, OPTM_None, OPA_AdSizeR, OPAP_None},
|
|
{OPT_Imm, OPS_Any, 0, 0, OPTM_None, OPA_JmpRel, OPAP_None},
|
|
{OPT_Creg, OPS_64, 0, 0, OPTM_None, OPA_AdSizeR, OPAP_None},
|
|
{OPT_Imm, OPS_Any, 0, 0, OPTM_Short, OPA_JmpRel, OPAP_None},
|
|
{OPT_Creg, OPS_16, 0, 0, OPTM_None, OPA_AdSizeR, OPAP_None},
|
|
{OPT_Imm, OPS_Any, 0, 0, OPTM_Short, OPA_JmpRel, OPAP_None},
|
|
{OPT_Creg, OPS_32, 0, 0, OPTM_None, OPA_AdSizeR, OPAP_None},
|
|
{OPT_Imm, OPS_Any, 0, 0, OPTM_Short, OPA_JmpRel, OPAP_None},
|
|
{OPT_Creg, OPS_64, 0, 0, OPTM_None, OPA_AdSizeR, OPAP_None},
|
|
{OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
|
|
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
|
|
{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_Mem, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Mem, OPS_80, 1, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_SegReg, OPS_16, 1, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_Areg, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
|
|
{OPT_Imm, OPS_16, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
|
|
{OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
|
|
{OPT_Imm, OPS_32, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
|
|
{OPT_Areg, OPS_64, 0, 0, OPTM_None, OPA_None, OPAP_None},
|
|
{OPT_Imm, OPS_32, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
|
|
{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_Mem, OPS_256, 1, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Imm, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_A16},
|
|
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
|
|
{OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
|
|
{OPT_RM, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None},
|
|
{OPT_RM, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None},
|
|
{OPT_RM, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Mem, OPS_80, 0, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Mem, OPS_16, 0, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Mem, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_Mem, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_MemEAX, OPS_Any, 0, 0, OPTM_None, OPA_None, OPAP_None},
|
|
{OPT_SS, OPS_Any, 0, 0, OPTM_None, OPA_None, OPAP_None},
|
|
{OPT_SS, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
|
|
{OPT_SS, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
|
|
{OPT_DS, OPS_Any, 0, 0, OPTM_None, OPA_None, OPAP_None},
|
|
{OPT_DS, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
|
|
{OPT_DS, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
|
|
{OPT_ES, OPS_Any, 0, 0, OPTM_None, OPA_None, OPAP_None},
|
|
{OPT_ES, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
|
|
{OPT_ES, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
|
|
{OPT_FS, OPS_Any, 0, 0, OPTM_None, OPA_None, OPAP_None},
|
|
{OPT_FS, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
|
|
{OPT_FS, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
|
|
{OPT_GS, OPS_Any, 0, 0, OPTM_None, OPA_None, OPAP_None},
|
|
{OPT_GS, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
|
|
{OPT_GS, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
|
|
{OPT_Mem, OPS_Any, 0, 0, OPTM_None, OPA_EA, OPAP_None},
|
|
{OPT_ImmNotSegOff, OPS_Any, 0, 0, OPTM_None, OPA_JmpRel, OPAP_None},
|
|
{OPT_ImmNotSegOff, OPS_16, 0, 0, OPTM_None, OPA_JmpRel, OPAP_None},
|
|
{OPT_ImmNotSegOff, OPS_32, 0, 0, OPTM_None, OPA_JmpRel, OPAP_None},
|
|
{OPT_Imm, OPS_16, 0, 0, OPTM_Near, OPA_JmpRel, OPAP_None},
|
|
{OPT_Imm, OPS_32, 0, 0, OPTM_Near, OPA_JmpRel, OPAP_None},
|
|
{OPT_Imm, OPS_Any, 0, 0, OPTM_Near, OPA_JmpRel, OPAP_None},
|
|
{OPT_RM, OPS_16, 0, 0, OPTM_Near, OPA_EA, OPAP_None},
|
|
{OPT_RM, OPS_32, 0, 0, OPTM_Near, OPA_EA, OPAP_None},
|
|
{OPT_RM, OPS_64, 0, 0, OPTM_Near, OPA_EA, OPAP_None},
|
|
{OPT_Mem, OPS_Any, 0, 0, OPTM_Near, OPA_EA, OPAP_None},
|
|
{OPT_Mem, OPS_16, 0, 0, OPTM_Far, OPA_EA, OPAP_None},
|
|
{OPT_Mem, OPS_32, 0, 0, OPTM_Far, OPA_EA, OPAP_None},
|
|
{OPT_Mem, OPS_64, 0, 0, OPTM_Far, OPA_EA, OPAP_None},
|
|
{OPT_Mem, OPS_Any, 0, 0, OPTM_Far, OPA_EA, OPAP_None},
|
|
{OPT_Imm, OPS_16, 0, 0, OPTM_Far, OPA_JmpFar, OPAP_None},
|
|
{OPT_Imm, OPS_32, 0, 0, OPTM_Far, OPA_JmpFar, OPAP_None},
|
|
{OPT_Imm, OPS_Any, 0, 0, OPTM_Far, OPA_JmpFar, OPAP_None},
|
|
{OPT_Imm, OPS_16, 0, 0, OPTM_None, OPA_JmpFar, OPAP_None},
|
|
{OPT_Imm, OPS_32, 0, 0, OPTM_None, OPA_JmpFar, OPAP_None},
|
|
{OPT_Imm, OPS_Any, 0, 0, OPTM_None, OPA_JmpFar, OPAP_None},
|
|
{OPT_Reg, OPS_80, 0, 0, OPTM_To, OPA_Op1Add, OPAP_None},
|
|
{OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Op1Add, OPAP_None},
|
|
{OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Op1Add, OPAP_None},
|
|
{OPT_Imm, OPS_16, 0, 0, OPTM_None, OPA_JmpRel, OPAP_None},
|
|
{OPT_Imm, OPS_32, 0, 0, OPTM_None, OPA_JmpRel, OPAP_None},
|
|
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_SImm, OPAP_None},
|
|
{OPT_Imm, OPS_BITS, 1, 0, OPTM_None, OPA_Imm, OPAP_SImm8},
|
|
{OPT_Imm, OPS_32, 0, 0, OPTM_None, OPA_SImm, OPAP_None},
|
|
{OPT_CS, OPS_Any, 0, 0, OPTM_None, OPA_None, OPAP_None},
|
|
{OPT_CS, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
|
|
{OPT_CS, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None}
|
|
};
|
|
|
|
static const x86_insn_info empty_insn[] = {
|
|
{ 0, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0 }
|
|
};
|
|
|
|
static const x86_insn_info not64_insn[] = {
|
|
{ 0, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0 }
|
|
};
|
|
|
|
static const x86_insn_info onebyte_insn[] = {
|
|
{ 0, 0, 0, 0, 0, {MOD_Op0Add, MOD_OpSizeR, MOD_DOpS64R}, 0, 0, 0, 1, {0x00, 0, 0}, 0, 0, 0 }
|
|
};
|
|
|
|
static const x86_insn_info onebyte_prefix_insn[] = {
|
|
{ 0, 0, 0, 0, 0, {MOD_PreAdd, MOD_Op0Add, 0}, 0, 0, 0x00, 1, {0x00, 0, 0}, 0, 0, 0 }
|
|
};
|
|
|
|
static const x86_insn_info twobyte_insn[] = {
|
|
{ SUF_L|SUF_Q, 0, 0, 0, 0, {MOD_Op0Add, MOD_Op1Add, 0}, 0, 0, 0, 2, {0x00, 0x00, 0}, 0, 0, 0 }
|
|
};
|
|
|
|
static const x86_insn_info threebyte_insn[] = {
|
|
{ 0, 0, 0, 0, 0, {MOD_Op0Add, MOD_Op1Add, MOD_Op2Add}, 0, 0, 0, 3, {0x00, 0x00, 0x00}, 0, 0, 0 }
|
|
};
|
|
|
|
static const x86_insn_info onebytemem_insn[] = {
|
|
{ SUF_L|SUF_Q|SUF_S, 0, 0, 0, 0, {MOD_SpAdd, MOD_Op0Add, 0}, 0, 0, 0, 1, {0x00, 0, 0}, 0, 1, 590 }
|
|
};
|
|
|
|
static const x86_insn_info twobytemem_insn[] = {
|
|
{ SUF_L|SUF_Q|SUF_S|SUF_W, 0, 0, 0, 0, {MOD_SpAdd, MOD_Op0Add, MOD_Op1Add}, 0, 0, 0, 2, {0x00, 0x00, 0}, 0, 1, 465 }
|
|
};
|
|
|
|
static const x86_insn_info mov_insn[] = {
|
|
{ SUF_B, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xA0, 0, 0}, 0, 2, 330 },
|
|
{ SUF_W, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 332 },
|
|
{ SUF_L, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 334 },
|
|
{ SUF_B, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xA2, 0, 0}, 0, 2, 336 },
|
|
{ SUF_W, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 338 },
|
|
{ SUF_L, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 340 },
|
|
{ 0, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xA0, 0, 0}, 0, 2, 306 },
|
|
{ 0, ONLY_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 308 },
|
|
{ 0, ONLY_64, 0, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 310 },
|
|
{ 0, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 312 },
|
|
{ 0, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xA2, 0, 0}, 0, 2, 314 },
|
|
{ 0, ONLY_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 316 },
|
|
{ 0, ONLY_64, 0, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 318 },
|
|
{ 0, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 320 },
|
|
{ SUF_B, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x88, 0xA2, 0}, 0, 2, 342 },
|
|
{ SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x89, 0xA3, 0}, 0, 2, 344 },
|
|
{ SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x89, 0xA3, 0}, 0, 2, 346 },
|
|
{ SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x89, 0xA3, 0}, 0, 2, 348 },
|
|
{ SUF_B, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x88, 0, 0}, 0, 2, 288 },
|
|
{ SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x89, 0, 0}, 0, 2, 228 },
|
|
{ SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x89, 0, 0}, 0, 2, 234 },
|
|
{ SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x89, 0, 0}, 0, 2, 240 },
|
|
{ SUF_B, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x8A, 0xA0, 0}, 0, 2, 350 },
|
|
{ SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x8B, 0xA1, 0}, 0, 2, 352 },
|
|
{ SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x8B, 0xA1, 0}, 0, 2, 354 },
|
|
{ SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x8B, 0xA1, 0}, 0, 2, 356 },
|
|
{ SUF_B, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x8A, 0, 0}, 0, 2, 290 },
|
|
{ SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x8B, 0, 0}, 0, 2, 114 },
|
|
{ SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x8B, 0, 0}, 0, 2, 117 },
|
|
{ SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x8B, 0, 0}, 0, 2, 120 },
|
|
{ SUF_W, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x8C, 0, 0}, 0, 2, 358 },
|
|
{ SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x8C, 0, 0}, 0, 2, 360 },
|
|
{ SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x8C, 0, 0}, 0, 2, 362 },
|
|
{ SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x8C, 0, 0}, 0, 2, 364 },
|
|
{ SUF_W, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x8E, 0, 0}, 0, 2, 366 },
|
|
{ SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x8E, 0, 0}, 0, 2, 361 },
|
|
{ SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x8E, 0, 0}, 0, 2, 363 },
|
|
{ SUF_B, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xB0, 0, 0}, 0, 2, 368 },
|
|
{ SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xB8, 0, 0}, 0, 2, 370 },
|
|
{ SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xB8, 0, 0}, 0, 2, 372 },
|
|
{ GAS_ILLEGAL, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xB8, 0, 0}, 0, 2, 374 },
|
|
{ SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xB8, 0xC7, 0}, 0, 2, 376 },
|
|
{ SUF_B, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xC6, 0, 0}, 0, 2, 378 },
|
|
{ SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xC7, 0, 0}, 0, 2, 380 },
|
|
{ SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xC7, 0, 0}, 0, 2, 382 },
|
|
{ SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xC7, 0, 0}, 0, 2, 384 },
|
|
{ SUF_B, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xC6, 0, 0}, 0, 2, 386 },
|
|
{ SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xC7, 0, 0}, 0, 2, 388 },
|
|
{ SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xC7, 0, 0}, 0, 2, 390 },
|
|
{ SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xC7, 0, 0}, 0, 2, 392 },
|
|
{ SUF_L, NOT_64, CPU_586, CPU_Priv, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x22, 0}, 0, 2, 394 },
|
|
{ SUF_L, NOT_64, CPU_386, CPU_Priv, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x22, 0}, 0, 2, 396 },
|
|
{ SUF_Q, ONLY_64, CPU_Priv, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x22, 0}, 0, 2, 398 },
|
|
{ SUF_L, NOT_64, CPU_586, CPU_Priv, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x20, 0}, 0, 2, 400 },
|
|
{ SUF_L, NOT_64, CPU_386, CPU_Priv, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x20, 0}, 0, 2, 395 },
|
|
{ SUF_Q, ONLY_64, CPU_Priv, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x20, 0}, 0, 2, 402 },
|
|
{ SUF_L, NOT_64, CPU_386, CPU_Priv, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x23, 0}, 0, 2, 404 },
|
|
{ SUF_Q, ONLY_64, CPU_Priv, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x23, 0}, 0, 2, 406 },
|
|
{ SUF_L, NOT_64, CPU_386, CPU_Priv, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x21, 0}, 0, 2, 405 },
|
|
{ SUF_Q, ONLY_64, CPU_Priv, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x21, 0}, 0, 2, 408 },
|
|
{ GAS_ONLY|SUF_Q, 0, CPU_MMX, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x6F, 0}, 0, 2, 213 },
|
|
{ GAS_ONLY|SUF_Q, ONLY_64, CPU_MMX, 0, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0x6E, 0}, 0, 2, 260 },
|
|
{ GAS_ONLY|SUF_Q, 0, CPU_MMX, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x7F, 0}, 0, 2, 296 },
|
|
{ GAS_ONLY|SUF_Q, ONLY_64, CPU_MMX, 0, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0x7E, 0}, 0, 2, 262 },
|
|
{ GAS_ONLY|SUF_Q, 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0xF3, 2, {0x0F, 0x7E, 0}, 0, 2, 88 },
|
|
{ GAS_ONLY|SUF_Q, 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0xF3, 2, {0x0F, 0x7E, 0}, 0, 2, 298 },
|
|
{ GAS_ONLY|SUF_Q, ONLY_64, CPU_SSE2, 0, 0, {0, 0, 0}, 64, 0, 0x66, 2, {0x0F, 0x6E, 0}, 0, 2, 266 },
|
|
{ GAS_ONLY|SUF_Q, 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0xD6, 0}, 0, 2, 300 },
|
|
{ GAS_ONLY|SUF_Q, ONLY_64, CPU_SSE2, 0, 0, {0, 0, 0}, 64, 0, 0x66, 2, {0x0F, 0x7E, 0}, 0, 2, 183 }
|
|
};
|
|
|
|
static const x86_insn_info movabs_insn[] = {
|
|
{ SUF_B, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xA0, 0, 0}, 0, 2, 306 },
|
|
{ SUF_W, ONLY_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 308 },
|
|
{ SUF_L, ONLY_64, 0, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 310 },
|
|
{ SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 312 },
|
|
{ SUF_B, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xA2, 0, 0}, 0, 2, 314 },
|
|
{ SUF_W, ONLY_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 316 },
|
|
{ SUF_L, ONLY_64, 0, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 318 },
|
|
{ SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 320 },
|
|
{ SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xB8, 0, 0}, 0, 2, 322 }
|
|
};
|
|
|
|
static const x86_insn_info movszx_insn[] = {
|
|
{ SUF_B, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 524 },
|
|
{ SUF_B, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 470 },
|
|
{ SUF_B, ONLY_64, 0, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 474 },
|
|
{ SUF_W, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, 472 },
|
|
{ SUF_W, ONLY_64, 0, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, 526 }
|
|
};
|
|
|
|
static const x86_insn_info movsxd_insn[] = {
|
|
{ SUF_L, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x63, 0, 0}, 0, 2, 564 }
|
|
};
|
|
|
|
static const x86_insn_info push_insn[] = {
|
|
{ SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 1, {0x50, 0, 0}, 0, 1, 370 },
|
|
{ SUF_L, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x50, 0, 0}, 0, 1, 372 },
|
|
{ SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0x50, 0, 0}, 0, 1, 322 },
|
|
{ SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 1, {0xFF, 0, 0}, 6, 1, 252 },
|
|
{ SUF_L, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xFF, 0, 0}, 6, 1, 248 },
|
|
{ SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0xFF, 0, 0}, 6, 1, 251 },
|
|
{ GAS_ILLEGAL, 0, CPU_186, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0x6A, 0, 0}, 0, 1, 116 },
|
|
{ GAS_ONLY, 0, CPU_186, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0x6A, 0, 0}, 0, 1, 616 },
|
|
{ SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 64, 0, 1, {0x6A, 0x68, 0}, 0, 1, 128 },
|
|
{ GAS_ILLEGAL, NOT_64, CPU_186, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x6A, 0x68, 0}, 0, 1, 617 },
|
|
{ SUF_W, 0, CPU_186, 0, 0, {0, 0, 0}, 16, 64, 0, 1, {0x6A, 0x68, 0}, 0, 1, 495 },
|
|
{ SUF_L, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x6A, 0x68, 0}, 0, 1, 497 },
|
|
{ GAS_ILLEGAL, 0, CPU_186, 0, 0, {0, 0, 0}, 16, 64, 0, 1, {0x68, 0, 0}, 0, 1, 381 },
|
|
{ GAS_ILLEGAL, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x68, 0, 0}, 0, 1, 383 },
|
|
{ GAS_ILLEGAL, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 64, 0, 1, {0x68, 0, 0}, 0, 1, 618 },
|
|
{ 0, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x0E, 0, 0}, 0, 1, 619 },
|
|
{ SUF_W, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x0E, 0, 0}, 0, 1, 620 },
|
|
{ SUF_L, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x0E, 0, 0}, 0, 1, 621 },
|
|
{ 0, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x16, 0, 0}, 0, 1, 575 },
|
|
{ SUF_W, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x16, 0, 0}, 0, 1, 576 },
|
|
{ SUF_L, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x16, 0, 0}, 0, 1, 577 },
|
|
{ 0, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x1E, 0, 0}, 0, 1, 578 },
|
|
{ SUF_W, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x1E, 0, 0}, 0, 1, 579 },
|
|
{ SUF_L, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x1E, 0, 0}, 0, 1, 580 },
|
|
{ 0, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x06, 0, 0}, 0, 1, 581 },
|
|
{ SUF_W, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x06, 0, 0}, 0, 1, 582 },
|
|
{ SUF_L, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x06, 0, 0}, 0, 1, 583 },
|
|
{ 0, 0, CPU_386, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xA0, 0}, 0, 1, 584 },
|
|
{ SUF_W, 0, CPU_386, 0, 0, {0, 0, 0}, 16, 0, 0, 2, {0x0F, 0xA0, 0}, 0, 1, 585 },
|
|
{ SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0xA0, 0}, 0, 1, 586 },
|
|
{ 0, 0, CPU_386, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xA8, 0}, 0, 1, 587 },
|
|
{ SUF_W, 0, CPU_386, 0, 0, {0, 0, 0}, 16, 0, 0, 2, {0x0F, 0xA8, 0}, 0, 1, 588 },
|
|
{ SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0xA8, 0}, 0, 1, 589 }
|
|
};
|
|
|
|
static const x86_insn_info pop_insn[] = {
|
|
{ SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 1, {0x58, 0, 0}, 0, 1, 370 },
|
|
{ SUF_L, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x58, 0, 0}, 0, 1, 372 },
|
|
{ SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0x58, 0, 0}, 0, 1, 322 },
|
|
{ SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 1, {0x8F, 0, 0}, 0, 1, 252 },
|
|
{ SUF_L, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x8F, 0, 0}, 0, 1, 248 },
|
|
{ SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0x8F, 0, 0}, 0, 1, 251 },
|
|
{ 0, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x17, 0, 0}, 0, 1, 575 },
|
|
{ 0, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x17, 0, 0}, 0, 1, 576 },
|
|
{ 0, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x17, 0, 0}, 0, 1, 577 },
|
|
{ 0, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x1F, 0, 0}, 0, 1, 578 },
|
|
{ 0, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x1F, 0, 0}, 0, 1, 579 },
|
|
{ 0, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x1F, 0, 0}, 0, 1, 580 },
|
|
{ 0, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x07, 0, 0}, 0, 1, 581 },
|
|
{ 0, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x07, 0, 0}, 0, 1, 582 },
|
|
{ 0, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x07, 0, 0}, 0, 1, 583 },
|
|
{ 0, 0, CPU_386, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xA1, 0}, 0, 1, 584 },
|
|
{ 0, 0, CPU_386, 0, 0, {0, 0, 0}, 16, 0, 0, 2, {0x0F, 0xA1, 0}, 0, 1, 585 },
|
|
{ 0, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0xA1, 0}, 0, 1, 586 },
|
|
{ 0, 0, CPU_386, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xA9, 0}, 0, 1, 587 },
|
|
{ 0, 0, CPU_386, 0, 0, {0, 0, 0}, 16, 0, 0, 2, {0x0F, 0xA9, 0}, 0, 1, 588 },
|
|
{ 0, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0xA9, 0}, 0, 1, 589 }
|
|
};
|
|
|
|
static const x86_insn_info xchg_insn[] = {
|
|
{ SUF_B, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x86, 0, 0}, 0, 2, 288 },
|
|
{ SUF_B, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x86, 0, 0}, 0, 2, 290 },
|
|
{ SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x90, 0, 0}, 0, 2, 450 },
|
|
{ SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x90, 0, 0}, 0, 2, 452 },
|
|
{ SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x87, 0, 0}, 0, 2, 228 },
|
|
{ SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x87, 0, 0}, 0, 2, 114 },
|
|
{ SUF_L, ONLY_64, 0, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x87, 0, 0}, 0, 2, 454 },
|
|
{ SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x90, 0, 0}, 0, 2, 456 },
|
|
{ SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x90, 0, 0}, 0, 2, 458 },
|
|
{ SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x87, 0, 0}, 0, 2, 234 },
|
|
{ SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x87, 0, 0}, 0, 2, 117 },
|
|
{ SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x90, 0, 0}, 0, 2, 460 },
|
|
{ SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x90, 0, 0}, 0, 2, 321 },
|
|
{ SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x90, 0, 0}, 0, 2, 462 },
|
|
{ SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x87, 0, 0}, 0, 2, 240 },
|
|
{ SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x87, 0, 0}, 0, 2, 120 }
|
|
};
|
|
|
|
static const x86_insn_info in_insn[] = {
|
|
{ SUF_B, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xE4, 0, 0}, 0, 2, 435 },
|
|
{ SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xE5, 0, 0}, 0, 2, 437 },
|
|
{ SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xE5, 0, 0}, 0, 2, 546 },
|
|
{ SUF_B, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xEC, 0, 0}, 0, 2, 441 },
|
|
{ SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xED, 0, 0}, 0, 2, 443 },
|
|
{ SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xED, 0, 0}, 0, 2, 439 },
|
|
{ GAS_ONLY|SUF_B, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xE4, 0, 0}, 0, 1, 3 },
|
|
{ GAS_ONLY|SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xE5, 0, 0}, 0, 1, 3 },
|
|
{ GAS_ONLY|SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xE5, 0, 0}, 0, 1, 3 },
|
|
{ GAS_ONLY|SUF_B, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xEC, 0, 0}, 0, 1, 440 },
|
|
{ GAS_ONLY|SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xED, 0, 0}, 0, 1, 440 },
|
|
{ GAS_ONLY|SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xED, 0, 0}, 0, 1, 440 }
|
|
};
|
|
|
|
static const x86_insn_info out_insn[] = {
|
|
{ SUF_B, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xE6, 0, 0}, 0, 2, 434 },
|
|
{ SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xE7, 0, 0}, 0, 2, 436 },
|
|
{ SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xE7, 0, 0}, 0, 2, 438 },
|
|
{ SUF_B, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xEE, 0, 0}, 0, 2, 440 },
|
|
{ SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xEF, 0, 0}, 0, 2, 442 },
|
|
{ SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xEF, 0, 0}, 0, 2, 444 },
|
|
{ GAS_ONLY|SUF_B, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xE6, 0, 0}, 0, 1, 3 },
|
|
{ GAS_ONLY|SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xE7, 0, 0}, 0, 1, 3 },
|
|
{ GAS_ONLY|SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xE7, 0, 0}, 0, 1, 3 },
|
|
{ GAS_ONLY|SUF_B, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xEE, 0, 0}, 0, 1, 440 },
|
|
{ GAS_ONLY|SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xEF, 0, 0}, 0, 1, 440 },
|
|
{ GAS_ONLY|SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xEF, 0, 0}, 0, 1, 440 }
|
|
};
|
|
|
|
static const x86_insn_info lea_insn[] = {
|
|
{ SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x8D, 0, 0}, 0, 2, 464 },
|
|
{ SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x8D, 0, 0}, 0, 2, 466 },
|
|
{ SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x8D, 0, 0}, 0, 2, 468 }
|
|
};
|
|
|
|
static const x86_insn_info ldes_insn[] = {
|
|
{ SUF_W, NOT_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 16, 0, 0, 1, {0x00, 0, 0}, 0, 2, 464 },
|
|
{ SUF_L, NOT_64, CPU_386, 0, 0, {MOD_Op0Add, 0, 0}, 32, 0, 0, 1, {0x00, 0, 0}, 0, 2, 466 }
|
|
};
|
|
|
|
static const x86_insn_info lfgss_insn[] = {
|
|
{ SUF_W, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 464 },
|
|
{ SUF_L, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 466 }
|
|
};
|
|
|
|
static const x86_insn_info arith_insn[] = {
|
|
{ SUF_B, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 1, {0x04, 0, 0}, 0, 2, 435 },
|
|
{ SUF_W, 0, 0, 0, 0, {MOD_Op2Add, MOD_Op1AddSp, 0}, 16, 0, 0, 2, {0x83, 0xC0, 0x05}, 0, 2, 494 },
|
|
{ SUF_L, 0, CPU_386, 0, 0, {MOD_Op2Add, MOD_Op1AddSp, 0}, 32, 0, 0, 2, {0x83, 0xC0, 0x05}, 0, 2, 496 },
|
|
{ SUF_Q, ONLY_64, 0, 0, 0, {MOD_Op2Add, MOD_Op1AddSp, 0}, 64, 0, 0, 2, {0x83, 0xC0, 0x05}, 0, 2, 498 },
|
|
{ SUF_B, 0, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 0, 0, 0, 1, {0x80, 0, 0}, 0, 2, 386 },
|
|
{ SUF_B, 0, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 0, 0, 0, 1, {0x80, 0, 0}, 0, 2, 378 },
|
|
{ SUF_W, 0, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 16, 0, 0, 1, {0x83, 0, 0}, 0, 2, 500 },
|
|
{ GAS_ILLEGAL, 0, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 16, 0, 0, 1, {0x83, 0x81, 0}, 0, 2, 502 },
|
|
{ SUF_W, 0, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 16, 0, 0, 1, {0x83, 0x81, 0}, 0, 2, 504 },
|
|
{ SUF_L, 0, CPU_386, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 32, 0, 0, 1, {0x83, 0, 0}, 0, 2, 506 },
|
|
{ GAS_ILLEGAL, NOT_64, CPU_386, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 32, 0, 0, 1, {0x83, 0x81, 0}, 0, 2, 508 },
|
|
{ SUF_L, 0, CPU_386, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 32, 0, 0, 1, {0x83, 0x81, 0}, 0, 2, 510 },
|
|
{ SUF_Q, ONLY_64, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 64, 0, 0, 1, {0x83, 0, 0}, 0, 2, 512 },
|
|
{ SUF_Q, ONLY_64, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 64, 0, 0, 1, {0x83, 0x81, 0}, 0, 2, 514 },
|
|
{ SUF_B, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 1, {0x00, 0, 0}, 0, 2, 288 },
|
|
{ SUF_W, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 16, 0, 0, 1, {0x01, 0, 0}, 0, 2, 228 },
|
|
{ SUF_L, 0, CPU_386, 0, 0, {MOD_Op0Add, 0, 0}, 32, 0, 0, 1, {0x01, 0, 0}, 0, 2, 234 },
|
|
{ SUF_Q, ONLY_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 64, 0, 0, 1, {0x01, 0, 0}, 0, 2, 240 },
|
|
{ SUF_B, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 1, {0x02, 0, 0}, 0, 2, 290 },
|
|
{ SUF_W, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 16, 0, 0, 1, {0x03, 0, 0}, 0, 2, 114 },
|
|
{ SUF_L, 0, CPU_386, 0, 0, {MOD_Op0Add, 0, 0}, 32, 0, 0, 1, {0x03, 0, 0}, 0, 2, 117 },
|
|
{ SUF_Q, ONLY_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 64, 0, 0, 1, {0x03, 0, 0}, 0, 2, 120 }
|
|
};
|
|
|
|
static const x86_insn_info incdec_insn[] = {
|
|
{ SUF_B, 0, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 0, 0, 0, 1, {0xFE, 0, 0}, 0, 1, 386 },
|
|
{ SUF_W, NOT_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 16, 0, 0, 1, {0x00, 0, 0}, 0, 1, 370 },
|
|
{ SUF_W, 0, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 16, 0, 0, 1, {0xFF, 0, 0}, 0, 1, 252 },
|
|
{ SUF_L, NOT_64, CPU_386, 0, 0, {MOD_Op0Add, 0, 0}, 32, 0, 0, 1, {0x00, 0, 0}, 0, 1, 372 },
|
|
{ SUF_L, 0, CPU_386, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 32, 0, 0, 1, {0xFF, 0, 0}, 0, 1, 248 },
|
|
{ SUF_Q, ONLY_64, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 64, 0, 0, 1, {0xFF, 0, 0}, 0, 1, 251 }
|
|
};
|
|
|
|
static const x86_insn_info f6_insn[] = {
|
|
{ SUF_B, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xF6, 0, 0}, 0, 1, 386 },
|
|
{ SUF_W, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 16, 0, 0, 1, {0xF7, 0, 0}, 0, 1, 252 },
|
|
{ SUF_L, 0, CPU_386, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0, 1, {0xF7, 0, 0}, 0, 1, 248 },
|
|
{ SUF_Q, ONLY_64, 0, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0, 1, {0xF7, 0, 0}, 0, 1, 251 }
|
|
};
|
|
|
|
static const x86_insn_info div_insn[] = {
|
|
{ SUF_B, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xF6, 0, 0}, 0, 1, 386 },
|
|
{ SUF_W, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 16, 0, 0, 1, {0xF7, 0, 0}, 0, 1, 252 },
|
|
{ SUF_L, 0, CPU_386, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0, 1, {0xF7, 0, 0}, 0, 1, 248 },
|
|
{ SUF_Q, ONLY_64, 0, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0, 1, {0xF7, 0, 0}, 0, 1, 251 },
|
|
{ SUF_B, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xF6, 0, 0}, 0, 2, 418 },
|
|
{ SUF_W, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 16, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 420 },
|
|
{ SUF_L, 0, CPU_386, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 422 },
|
|
{ SUF_Q, ONLY_64, 0, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 424 }
|
|
};
|
|
|
|
static const x86_insn_info test_insn[] = {
|
|
{ SUF_B, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xA8, 0, 0}, 0, 2, 435 },
|
|
{ SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xA9, 0, 0}, 0, 2, 552 },
|
|
{ SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xA9, 0, 0}, 0, 2, 554 },
|
|
{ SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xA9, 0, 0}, 0, 2, 556 },
|
|
{ SUF_B, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xF6, 0, 0}, 0, 2, 386 },
|
|
{ SUF_B, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xF6, 0, 0}, 0, 2, 378 },
|
|
{ SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 388 },
|
|
{ SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 380 },
|
|
{ SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 390 },
|
|
{ SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 382 },
|
|
{ SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 392 },
|
|
{ SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 384 },
|
|
{ SUF_B, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x84, 0, 0}, 0, 2, 288 },
|
|
{ SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x85, 0, 0}, 0, 2, 228 },
|
|
{ SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x85, 0, 0}, 0, 2, 234 },
|
|
{ SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x85, 0, 0}, 0, 2, 240 },
|
|
{ SUF_B, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x84, 0, 0}, 0, 2, 290 },
|
|
{ SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x85, 0, 0}, 0, 2, 114 },
|
|
{ SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x85, 0, 0}, 0, 2, 117 },
|
|
{ SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x85, 0, 0}, 0, 2, 120 }
|
|
};
|
|
|
|
static const x86_insn_info aadm_insn[] = {
|
|
{ 0, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 2, {0xD4, 0x0A, 0}, 0, 0, 0 },
|
|
{ 0, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 1, {0xD4, 0, 0}, 0, 1, 3 }
|
|
};
|
|
|
|
static const x86_insn_info imul_insn[] = {
|
|
{ SUF_B, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xF6, 0, 0}, 5, 1, 386 },
|
|
{ SUF_W, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xF7, 0, 0}, 5, 1, 252 },
|
|
{ SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xF7, 0, 0}, 5, 1, 248 },
|
|
{ SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xF7, 0, 0}, 5, 1, 251 },
|
|
{ SUF_W, 0, CPU_386, 0, 0, {0, 0, 0}, 16, 0, 0, 2, {0x0F, 0xAF, 0}, 0, 2, 114 },
|
|
{ SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0xAF, 0}, 0, 2, 117 },
|
|
{ SUF_Q, ONLY_64, CPU_386, 0, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0xAF, 0}, 0, 2, 120 },
|
|
{ SUF_W, 0, CPU_186, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x6B, 0, 0}, 0, 3, 114 },
|
|
{ SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x6B, 0, 0}, 0, 3, 117 },
|
|
{ SUF_Q, ONLY_64, CPU_186, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x6B, 0, 0}, 0, 3, 120 },
|
|
{ SUF_W, 0, CPU_186, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x6B, 0, 0}, 0, 2, 268 },
|
|
{ SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x6B, 0, 0}, 0, 2, 270 },
|
|
{ SUF_Q, ONLY_64, CPU_186, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x6B, 0, 0}, 0, 2, 272 },
|
|
{ SUF_W, 0, CPU_186, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x6B, 0x69, 0}, 0, 3, 123 },
|
|
{ SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x6B, 0x69, 0}, 0, 3, 126 },
|
|
{ SUF_Q, ONLY_64, CPU_186, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x6B, 0x69, 0}, 0, 3, 129 },
|
|
{ SUF_W, 0, CPU_186, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x6B, 0x69, 0}, 0, 2, 274 },
|
|
{ SUF_L, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x6B, 0x69, 0}, 0, 2, 276 },
|
|
{ SUF_Q, ONLY_64, CPU_186, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x6B, 0x69, 0}, 0, 2, 278 }
|
|
};
|
|
|
|
static const x86_insn_info shift_insn[] = {
|
|
{ SUF_B, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xD2, 0, 0}, 0, 2, 476 },
|
|
{ SUF_B, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xD0, 0, 0}, 0, 2, 478 },
|
|
{ SUF_B, 0, CPU_186, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xC0, 0, 0}, 0, 2, 386 },
|
|
{ SUF_W, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 16, 0, 0, 1, {0xD3, 0, 0}, 0, 2, 480 },
|
|
{ SUF_W, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 16, 0, 0, 1, {0xD1, 0, 0}, 0, 2, 482 },
|
|
{ SUF_W, 0, CPU_186, 0, 0, {MOD_SpAdd, 0, 0}, 16, 0, 0, 1, {0xC1, 0, 0}, 0, 2, 252 },
|
|
{ SUF_L, 0, CPU_386, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0, 1, {0xD3, 0, 0}, 0, 2, 484 },
|
|
{ SUF_L, 0, CPU_386, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0, 1, {0xD1, 0, 0}, 0, 2, 486 },
|
|
{ SUF_L, 0, CPU_386, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0, 1, {0xC1, 0, 0}, 0, 2, 254 },
|
|
{ SUF_Q, ONLY_64, 0, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0, 1, {0xD3, 0, 0}, 0, 2, 488 },
|
|
{ SUF_Q, ONLY_64, 0, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0, 1, {0xD1, 0, 0}, 0, 2, 490 },
|
|
{ SUF_Q, ONLY_64, CPU_186, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0, 1, {0xC1, 0, 0}, 0, 2, 256 },
|
|
{ GAS_ONLY|SUF_B, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xD0, 0, 0}, 0, 1, 386 },
|
|
{ GAS_ONLY|SUF_W, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 16, 0, 0, 1, {0xD1, 0, 0}, 0, 1, 252 },
|
|
{ GAS_ONLY|SUF_L, 0, CPU_386, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0, 1, {0xD1, 0, 0}, 0, 1, 248 },
|
|
{ GAS_ONLY|SUF_Q, ONLY_64, 0, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0, 1, {0xD1, 0, 0}, 0, 1, 251 }
|
|
};
|
|
|
|
static const x86_insn_info shlrd_insn[] = {
|
|
{ SUF_W, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 2, {0x0F, 0x00, 0}, 0, 3, 228 },
|
|
{ SUF_W, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 2, {0x0F, 0x01, 0}, 0, 3, 231 },
|
|
{ SUF_L, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 2, {0x0F, 0x00, 0}, 0, 3, 234 },
|
|
{ SUF_L, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 2, {0x0F, 0x01, 0}, 0, 3, 237 },
|
|
{ SUF_Q, ONLY_64, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 2, {0x0F, 0x00, 0}, 0, 3, 240 },
|
|
{ SUF_Q, ONLY_64, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 2, {0x0F, 0x01, 0}, 0, 3, 243 },
|
|
{ GAS_ONLY|SUF_W, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, 228 },
|
|
{ GAS_ONLY|SUF_L, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, 234 },
|
|
{ GAS_ONLY|SUF_Q, ONLY_64, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, 240 }
|
|
};
|
|
|
|
static const x86_insn_info call_insn[] = {
|
|
{ 0, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, {0, 0, 0}, 0, 1, 591 },
|
|
{ 0, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, {0, 0, 0}, 0, 1, 592 },
|
|
{ 0, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, {0, 0, 0}, 0, 1, 593 },
|
|
{ 0, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, {0, 0, 0}, 0, 1, 593 },
|
|
{ 0, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 1, {0xE8, 0, 0}, 0, 1, 594 },
|
|
{ 0, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xE8, 0, 0}, 0, 1, 595 },
|
|
{ 0, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 64, 0, 1, {0xE8, 0, 0}, 0, 1, 595 },
|
|
{ 0, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0xE8, 0, 0}, 0, 1, 596 },
|
|
{ 0, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xFF, 0, 0}, 2, 1, 252 },
|
|
{ 0, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xFF, 0, 0}, 2, 1, 248 },
|
|
{ 0, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 64, 0, 1, {0xFF, 0, 0}, 2, 1, 251 },
|
|
{ 0, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0xFF, 0, 0}, 2, 1, 590 },
|
|
{ 0, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 1, {0xFF, 0, 0}, 2, 1, 597 },
|
|
{ 0, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xFF, 0, 0}, 2, 1, 598 },
|
|
{ 0, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 64, 0, 1, {0xFF, 0, 0}, 2, 1, 599 },
|
|
{ 0, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0xFF, 0, 0}, 2, 1, 600 },
|
|
{ 0, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xFF, 0, 0}, 3, 1, 601 },
|
|
{ 0, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xFF, 0, 0}, 3, 1, 602 },
|
|
{ 0, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xFF, 0, 0}, 3, 1, 603 },
|
|
{ 0, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xFF, 0, 0}, 3, 1, 604 },
|
|
{ 0, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x9A, 0, 0}, 3, 1, 605 },
|
|
{ 0, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x9A, 0, 0}, 3, 1, 606 },
|
|
{ 0, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x9A, 0, 0}, 3, 1, 607 },
|
|
{ 0, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x9A, 0, 0}, 3, 1, 608 },
|
|
{ 0, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x9A, 0, 0}, 3, 1, 609 },
|
|
{ 0, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x9A, 0, 0}, 3, 1, 610 }
|
|
};
|
|
|
|
static const x86_insn_info jmp_insn[] = {
|
|
{ 0, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, {0, 0, 0}, 0, 1, 591 },
|
|
{ 0, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, {0, 0, 0}, 0, 1, 592 },
|
|
{ 0, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x00, 0, 0}, 0, 1, 593 },
|
|
{ 0, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x00, 0, 0}, 0, 1, 593 },
|
|
{ 0, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0xEB, 0, 0}, 0, 1, 538 },
|
|
{ 0, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 1, {0xE9, 0, 0}, 0, 1, 594 },
|
|
{ 0, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xE9, 0, 0}, 0, 1, 595 },
|
|
{ 0, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 64, 0, 1, {0xE9, 0, 0}, 0, 1, 595 },
|
|
{ 0, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0xE9, 0, 0}, 0, 1, 596 },
|
|
{ 0, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 1, {0xFF, 0, 0}, 4, 1, 252 },
|
|
{ 0, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xFF, 0, 0}, 4, 1, 248 },
|
|
{ 0, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 64, 0, 1, {0xFF, 0, 0}, 4, 1, 251 },
|
|
{ 0, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0xFF, 0, 0}, 4, 1, 590 },
|
|
{ 0, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 1, {0xFF, 0, 0}, 4, 1, 597 },
|
|
{ 0, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xFF, 0, 0}, 4, 1, 598 },
|
|
{ 0, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 64, 0, 1, {0xFF, 0, 0}, 4, 1, 599 },
|
|
{ 0, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0xFF, 0, 0}, 4, 1, 600 },
|
|
{ 0, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xFF, 0, 0}, 5, 1, 601 },
|
|
{ 0, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xFF, 0, 0}, 5, 1, 602 },
|
|
{ 0, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xFF, 0, 0}, 5, 1, 603 },
|
|
{ 0, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xFF, 0, 0}, 5, 1, 604 },
|
|
{ 0, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xEA, 0, 0}, 3, 1, 605 },
|
|
{ 0, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xEA, 0, 0}, 3, 1, 606 },
|
|
{ 0, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xEA, 0, 0}, 3, 1, 607 },
|
|
{ 0, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xEA, 0, 0}, 3, 1, 608 },
|
|
{ 0, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xEA, 0, 0}, 3, 1, 609 },
|
|
{ 0, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xEA, 0, 0}, 3, 1, 610 }
|
|
};
|
|
|
|
static const x86_insn_info retnf_insn[] = {
|
|
{ 0, NOT_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 1, {0x01, 0, 0}, 0, 0, 0 },
|
|
{ 0, NOT_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 1, {0x00, 0, 0}, 0, 1, 371 },
|
|
{ 0, ONLY_64, 0, 0, 0, {MOD_Op0Add, MOD_OpSizeR, 0}, 0, 0, 0, 1, {0x01, 0, 0}, 0, 0, 0 },
|
|
{ 0, ONLY_64, 0, 0, 0, {MOD_Op0Add, MOD_OpSizeR, 0}, 0, 0, 0, 1, {0x00, 0, 0}, 0, 1, 371 },
|
|
{ SUF_L|SUF_Q|SUF_W, 0, 0, 0, 0, {MOD_Op0Add, MOD_OpSizeR, 0}, 0, 0, 0, 1, {0x01, 0, 0}, 0, 0, 0 },
|
|
{ SUF_L|SUF_Q|SUF_W, 0, 0, 0, 0, {MOD_Op0Add, MOD_OpSizeR, 0}, 0, 0, 0, 1, {0x00, 0, 0}, 0, 1, 371 }
|
|
};
|
|
|
|
static const x86_insn_info enter_insn[] = {
|
|
{ GAS_NO_REV|SUF_L, NOT_64, CPU_186, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xC8, 0, 0}, 0, 2, 562 },
|
|
{ GAS_NO_REV|SUF_Q, ONLY_64, CPU_186, 0, 0, {0, 0, 0}, 64, 64, 0, 1, {0xC8, 0, 0}, 0, 2, 562 },
|
|
{ GAS_ONLY|GAS_NO_REV|SUF_W, 0, CPU_186, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xC8, 0, 0}, 0, 2, 562 }
|
|
};
|
|
|
|
static const x86_insn_info jcc_insn[] = {
|
|
{ 0, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, {0, 0, 0}, 0, 1, 532 },
|
|
{ 0, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 0, {0, 0, 0}, 0, 1, 614 },
|
|
{ 0, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 0, {0, 0, 0}, 0, 1, 615 },
|
|
{ 0, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 0, {0, 0, 0}, 0, 1, 615 },
|
|
{ 0, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 64, 0, 1, {0x70, 0, 0}, 0, 1, 538 },
|
|
{ 0, 0, CPU_186, 0, 0, {MOD_Op1Add, 0, 0}, 16, 64, 0, 2, {0x0F, 0x80, 0}, 0, 1, 594 },
|
|
{ 0, NOT_64, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 2, {0x0F, 0x80, 0}, 0, 1, 595 },
|
|
{ 0, ONLY_64, 0, 0, 0, {MOD_Op1Add, 0, 0}, 64, 64, 0, 2, {0x0F, 0x80, 0}, 0, 1, 595 },
|
|
{ 0, 0, CPU_186, 0, 0, {MOD_Op1Add, 0, 0}, 0, 64, 0, 2, {0x0F, 0x80, 0}, 0, 1, 596 }
|
|
};
|
|
|
|
static const x86_insn_info jcxz_insn[] = {
|
|
{ 0, 0, 0, 0, 0, {MOD_AdSizeR, 0, 0}, 0, 0, 0, 0, {0, 0, 0}, 0, 1, 532 },
|
|
{ 0, 0, 0, 0, 0, {MOD_AdSizeR, 0, 0}, 0, 64, 0, 1, {0xE3, 0, 0}, 0, 1, 538 }
|
|
};
|
|
|
|
static const x86_insn_info loop_insn[] = {
|
|
{ 0, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, {0, 0, 0}, 0, 1, 532 },
|
|
{ 0, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, {0, 0, 0}, 0, 2, 532 },
|
|
{ 0, 0, CPU_386, 0, 0, {0, 0, 0}, 0, 64, 0, 0, {0, 0, 0}, 0, 2, 534 },
|
|
{ 0, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 0, {0, 0, 0}, 0, 2, 536 },
|
|
{ 0, NOT_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 1, {0xE0, 0, 0}, 0, 1, 538 },
|
|
{ 0, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 64, 0, 1, {0xE0, 0, 0}, 0, 2, 538 },
|
|
{ 0, 0, CPU_386, 0, 0, {MOD_Op0Add, 0, 0}, 0, 64, 0, 1, {0xE0, 0, 0}, 0, 2, 540 },
|
|
{ 0, ONLY_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 64, 0, 1, {0xE0, 0, 0}, 0, 2, 542 }
|
|
};
|
|
|
|
static const x86_insn_info setcc_insn[] = {
|
|
{ SUF_B, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0x0F, 0x90, 0}, 2, 1, 288 }
|
|
};
|
|
|
|
static const x86_insn_info cmpsd_insn[] = {
|
|
{ GAS_ILLEGAL, NOT_AVX, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xA7, 0, 0}, 0, 0, 0 },
|
|
{ 0, 0, CPU_SSE2, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0xF2, 2, {0x0F, 0xC2, 0}, 0, 3, 108 },
|
|
{ 0, 0, CPU_SSE2, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0xF2, 2, {0x0F, 0xC2, 0}, 0, 3, 111 },
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC3, 2, {0x0F, 0xC2, 0}, 0, 4, 0 },
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC3, 2, {0x0F, 0xC2, 0}, 0, 4, 4 }
|
|
};
|
|
|
|
static const x86_insn_info movsd_insn[] = {
|
|
{ 0, NOT_AVX, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xA5, 0, 0}, 0, 0, 0 },
|
|
{ 0, 0, CPU_SSE2, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0xF2, 2, {0x0F, 0x10, 0}, 0, 2, 108 },
|
|
{ 0, 0, CPU_SSE2, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0xF2, 2, {0x0F, 0x10, 0}, 0, 2, 216 },
|
|
{ 0, 0, CPU_SSE2, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0xF2, 2, {0x0F, 0x11, 0}, 0, 2, 39 },
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC3, 2, {0x0F, 0x10, 0}, 0, 3, 0 }
|
|
};
|
|
|
|
static const x86_insn_info bittest_insn[] = {
|
|
{ SUF_W, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 228 },
|
|
{ SUF_L, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 234 },
|
|
{ SUF_Q, ONLY_64, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 240 },
|
|
{ SUF_W, 0, CPU_386, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 16, 0, 0, 2, {0x0F, 0xBA, 0}, 0, 2, 252 },
|
|
{ SUF_L, 0, CPU_386, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 32, 0, 0, 2, {0x0F, 0xBA, 0}, 0, 2, 254 },
|
|
{ SUF_Q, ONLY_64, CPU_386, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 64, 0, 0, 2, {0x0F, 0xBA, 0}, 0, 2, 256 }
|
|
};
|
|
|
|
static const x86_insn_info bsfr_insn[] = {
|
|
{ SUF_W, 0, 0, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 114 },
|
|
{ SUF_L, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 117 },
|
|
{ SUF_Q, ONLY_64, 0, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 120 }
|
|
};
|
|
|
|
static const x86_insn_info int_insn[] = {
|
|
{ 0, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xCD, 0, 0}, 0, 1, 3 }
|
|
};
|
|
|
|
static const x86_insn_info bound_insn[] = {
|
|
{ SUF_W, NOT_64, CPU_186, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x62, 0, 0}, 0, 2, 414 },
|
|
{ SUF_L, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x62, 0, 0}, 0, 2, 324 }
|
|
};
|
|
|
|
static const x86_insn_info arpl_insn[] = {
|
|
{ SUF_W, NOT_64, CPU_286, CPU_Prot, 0, {0, 0, 0}, 0, 0, 0, 1, {0x63, 0, 0}, 0, 2, 228 }
|
|
};
|
|
|
|
static const x86_insn_info str_insn[] = {
|
|
{ SUF_W, 0, CPU_286, CPU_Prot, 0, {0, 0, 0}, 16, 0, 0, 2, {0x0F, 0x00, 0}, 1, 1, 360 },
|
|
{ SUF_L, 0, CPU_386, CPU_Prot, 0, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0x00, 0}, 1, 1, 14 },
|
|
{ SUF_Q, ONLY_64, CPU_286, CPU_Prot, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0x00, 0}, 1, 1, 18 },
|
|
{ SUF_L|SUF_W, 0, CPU_286, CPU_Prot, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 1, 1, 115 }
|
|
};
|
|
|
|
static const x86_insn_info prot286_insn[] = {
|
|
{ SUF_W, 0, CPU_286, 0, 0, {MOD_SpAdd, MOD_Op1Add, 0}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 1, 115 }
|
|
};
|
|
|
|
static const x86_insn_info sldtmsw_insn[] = {
|
|
{ SUF_W, 0, CPU_286, 0, 0, {MOD_SpAdd, MOD_Op1Add, 0}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 1, 22 },
|
|
{ SUF_L, 0, CPU_386, 0, 0, {MOD_SpAdd, MOD_Op1Add, 0}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 1, 50 },
|
|
{ SUF_Q, ONLY_64, CPU_286, 0, 0, {MOD_SpAdd, MOD_Op1Add, 0}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 1, 6 },
|
|
{ SUF_W, 0, CPU_286, 0, 0, {MOD_SpAdd, MOD_Op1Add, 0}, 16, 0, 0, 2, {0x0F, 0x00, 0}, 0, 1, 360 },
|
|
{ SUF_L, 0, CPU_386, 0, 0, {MOD_SpAdd, MOD_Op1Add, 0}, 32, 0, 0, 2, {0x0F, 0x00, 0}, 0, 1, 14 },
|
|
{ SUF_Q, ONLY_64, CPU_286, 0, 0, {MOD_SpAdd, MOD_Op1Add, 0}, 64, 0, 0, 2, {0x0F, 0x00, 0}, 0, 1, 18 }
|
|
};
|
|
|
|
static const x86_insn_info fld_insn[] = {
|
|
{ SUF_S, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xD9, 0, 0}, 0, 1, 572 },
|
|
{ SUF_L, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xDD, 0, 0}, 0, 1, 573 },
|
|
{ 0, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xDB, 0, 0}, 5, 1, 570 },
|
|
{ 0, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0xD9, 0xC0, 0}, 0, 1, 293 }
|
|
};
|
|
|
|
static const x86_insn_info fstp_insn[] = {
|
|
{ SUF_S, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xD9, 0, 0}, 3, 1, 572 },
|
|
{ SUF_L, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xDD, 0, 0}, 3, 1, 573 },
|
|
{ 0, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xDB, 0, 0}, 7, 1, 570 },
|
|
{ 0, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0xDD, 0xD8, 0}, 0, 1, 293 }
|
|
};
|
|
|
|
static const x86_insn_info fldstpt_insn[] = {
|
|
{ 0, 0, CPU_FPU, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xDB, 0, 0}, 0, 1, 570 }
|
|
};
|
|
|
|
static const x86_insn_info fildstp_insn[] = {
|
|
{ SUF_S, 0, CPU_FPU, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xDF, 0, 0}, 0, 1, 571 },
|
|
{ SUF_L, 0, CPU_FPU, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xDB, 0, 0}, 0, 1, 572 },
|
|
{ SUF_Q, 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_Op0Add, MOD_SpAdd}, 0, 0, 0, 1, {0xDD, 0, 0}, 0, 1, 573 },
|
|
{ GAS_ONLY, 0, CPU_FPU, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xDF, 0, 0}, 0, 1, 22 }
|
|
};
|
|
|
|
static const x86_insn_info fbldstp_insn[] = {
|
|
{ 0, 0, CPU_FPU, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xDF, 0, 0}, 0, 1, 493 }
|
|
};
|
|
|
|
static const x86_insn_info fst_insn[] = {
|
|
{ SUF_S, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xD9, 0, 0}, 2, 1, 572 },
|
|
{ SUF_L, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xDD, 0, 0}, 2, 1, 573 },
|
|
{ 0, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0xDD, 0xD0, 0}, 0, 1, 293 }
|
|
};
|
|
|
|
static const x86_insn_info fxch_insn[] = {
|
|
{ 0, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0xD9, 0xC8, 0}, 0, 1, 293 },
|
|
{ 0, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0xD9, 0xC8, 0}, 0, 2, 292 },
|
|
{ 0, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0xD9, 0xC8, 0}, 0, 2, 294 },
|
|
{ 0, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0xD9, 0xC9, 0}, 0, 0, 0 }
|
|
};
|
|
|
|
static const x86_insn_info fcom_insn[] = {
|
|
{ SUF_S, 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 0, 0, 0, 1, {0xD8, 0, 0}, 0, 1, 572 },
|
|
{ SUF_L, 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 0, 0, 0, 1, {0xDC, 0, 0}, 0, 1, 573 },
|
|
{ 0, 0, CPU_FPU, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0xD8, 0x00, 0}, 0, 1, 293 },
|
|
{ GAS_ONLY, 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 0, 0, 0, 1, {0xD8, 0, 0}, 0, 1, 50 },
|
|
{ GAS_ONLY, 0, CPU_FPU, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0xD8, 0x01, 0}, 0, 0, 0 },
|
|
{ GAS_ILLEGAL, 0, CPU_FPU, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0xD8, 0x00, 0}, 0, 2, 292 }
|
|
};
|
|
|
|
static const x86_insn_info fcom2_insn[] = {
|
|
{ 0, 0, CPU_286, CPU_FPU, 0, {MOD_Op0Add, MOD_Op1Add, 0}, 0, 0, 0, 2, {0x00, 0x00, 0}, 0, 1, 293 },
|
|
{ 0, 0, CPU_286, CPU_FPU, 0, {MOD_Op0Add, MOD_Op1Add, 0}, 0, 0, 0, 2, {0x00, 0x00, 0}, 0, 2, 292 }
|
|
};
|
|
|
|
static const x86_insn_info farith_insn[] = {
|
|
{ SUF_S, 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_Gap, MOD_SpAdd}, 0, 0, 0, 1, {0xD8, 0, 0}, 0, 1, 572 },
|
|
{ SUF_L, 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_Gap, MOD_SpAdd}, 0, 0, 0, 1, {0xDC, 0, 0}, 0, 1, 573 },
|
|
{ 0, 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_Op1Add, 0}, 0, 0, 0, 2, {0xD8, 0x00, 0}, 0, 1, 293 },
|
|
{ 0, 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_Op1Add, 0}, 0, 0, 0, 2, {0xD8, 0x00, 0}, 0, 2, 292 },
|
|
{ 0, 0, CPU_FPU, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0xDC, 0x00, 0}, 0, 1, 611 },
|
|
{ GAS_ILLEGAL, 0, CPU_FPU, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0xDC, 0x00, 0}, 0, 2, 294 },
|
|
{ GAS_ONLY, 0, CPU_FPU, 0, 0, {MOD_Gap, MOD_Op1Add, 0}, 0, 0, 0, 2, {0xDC, 0x00, 0}, 0, 2, 294 }
|
|
};
|
|
|
|
static const x86_insn_info farithp_insn[] = {
|
|
{ 0, 0, CPU_FPU, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0xDE, 0x01, 0}, 0, 0, 0 },
|
|
{ 0, 0, CPU_FPU, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0xDE, 0x00, 0}, 0, 1, 293 },
|
|
{ 0, 0, CPU_FPU, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0xDE, 0x00, 0}, 0, 2, 294 }
|
|
};
|
|
|
|
static const x86_insn_info fiarith_insn[] = {
|
|
{ SUF_S, 0, CPU_FPU, 0, 0, {MOD_SpAdd, MOD_Op0Add, 0}, 0, 0, 0, 1, {0x04, 0, 0}, 0, 1, 571 },
|
|
{ SUF_L, 0, CPU_FPU, 0, 0, {MOD_SpAdd, MOD_Op0Add, 0}, 0, 0, 0, 1, {0x00, 0, 0}, 0, 1, 572 }
|
|
};
|
|
|
|
static const x86_insn_info fldnstcw_insn[] = {
|
|
{ SUF_W, 0, CPU_FPU, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xD9, 0, 0}, 0, 1, 22 }
|
|
};
|
|
|
|
static const x86_insn_info fstcw_insn[] = {
|
|
{ SUF_W, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x9B, 0xD9, 0}, 7, 1, 22 }
|
|
};
|
|
|
|
static const x86_insn_info fnstsw_insn[] = {
|
|
{ SUF_W, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xDD, 0, 0}, 7, 1, 22 },
|
|
{ SUF_W, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0xDF, 0xE0, 0}, 0, 1, 308 }
|
|
};
|
|
|
|
static const x86_insn_info fstsw_insn[] = {
|
|
{ SUF_W, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x9B, 0xDD, 0}, 7, 1, 22 },
|
|
{ SUF_W, 0, CPU_FPU, 0, 0, {0, 0, 0}, 0, 0, 0, 3, {0x9B, 0xDF, 0xE0}, 0, 1, 308 }
|
|
};
|
|
|
|
static const x86_insn_info ffree_insn[] = {
|
|
{ 0, 0, CPU_FPU, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 2, {0x00, 0xC0, 0}, 0, 1, 293 }
|
|
};
|
|
|
|
static const x86_insn_info bswap_insn[] = {
|
|
{ SUF_L, 0, CPU_486, 0, 0, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0xC8, 0}, 0, 1, 612 },
|
|
{ SUF_Q, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0xC8, 0}, 0, 1, 613 }
|
|
};
|
|
|
|
static const x86_insn_info cmpxchgxadd_insn[] = {
|
|
{ SUF_B, 0, CPU_486, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 288 },
|
|
{ SUF_W, 0, CPU_486, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, 228 },
|
|
{ SUF_L, 0, CPU_486, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, 234 },
|
|
{ SUF_Q, ONLY_64, CPU_486, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, 240 }
|
|
};
|
|
|
|
static const x86_insn_info cmpxchg8b_insn[] = {
|
|
{ SUF_Q, 0, CPU_586, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xC7, 0}, 1, 1, 6 }
|
|
};
|
|
|
|
static const x86_insn_info cmovcc_insn[] = {
|
|
{ SUF_W, 0, CPU_686, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 2, {0x0F, 0x40, 0}, 0, 2, 114 },
|
|
{ SUF_L, 0, CPU_686, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 2, {0x0F, 0x40, 0}, 0, 2, 117 },
|
|
{ SUF_Q, ONLY_64, CPU_686, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 2, {0x0F, 0x40, 0}, 0, 2, 120 }
|
|
};
|
|
|
|
static const x86_insn_info fcmovcc_insn[] = {
|
|
{ 0, 0, CPU_686, CPU_FPU, 0, {MOD_Op0Add, MOD_Op1Add, 0}, 0, 0, 0, 2, {0x00, 0x00, 0}, 0, 2, 292 }
|
|
};
|
|
|
|
static const x86_insn_info movnti_insn[] = {
|
|
{ SUF_L, 0, CPU_P4, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xC3, 0}, 0, 2, 302 },
|
|
{ SUF_Q, ONLY_64, CPU_P4, 0, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0xC3, 0}, 0, 2, 304 }
|
|
};
|
|
|
|
static const x86_insn_info clflush_insn[] = {
|
|
{ 0, 0, CPU_P3, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xAE, 0}, 7, 1, 42 }
|
|
};
|
|
|
|
static const x86_insn_info movd_insn[] = {
|
|
{ 0, 0, CPU_386, CPU_MMX, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x6E, 0}, 0, 2, 258 },
|
|
{ 0, ONLY_64, CPU_MMX, 0, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0x6E, 0}, 0, 2, 260 },
|
|
{ 0, 0, CPU_386, CPU_MMX, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x7E, 0}, 0, 2, 259 },
|
|
{ 0, ONLY_64, CPU_MMX, 0, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0x7E, 0}, 0, 2, 262 },
|
|
{ 0, 0, CPU_386, CPU_SSE2, 0, {0, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0x6E, 0}, 0, 2, 264 },
|
|
{ 0, ONLY_64, CPU_SSE2, 0, 0, {0, 0, 0}, 64, 0, 0x66, 2, {0x0F, 0x6E, 0}, 0, 2, 266 },
|
|
{ 0, 0, CPU_386, CPU_SSE2, 0, {0, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0x7E, 0}, 0, 2, 189 },
|
|
{ 0, ONLY_64, CPU_SSE2, 0, 0, {0, 0, 0}, 64, 0, 0x66, 2, {0x0F, 0x7E, 0}, 0, 2, 183 }
|
|
};
|
|
|
|
static const x86_insn_info movq_insn[] = {
|
|
{ GAS_ILLEGAL, 0, CPU_MMX, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x6F, 0}, 0, 2, 213 },
|
|
{ GAS_ILLEGAL, ONLY_64, CPU_MMX, 0, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0x6E, 0}, 0, 2, 260 },
|
|
{ GAS_ILLEGAL, 0, CPU_MMX, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x7F, 0}, 0, 2, 296 },
|
|
{ GAS_ILLEGAL, ONLY_64, CPU_MMX, 0, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0x7E, 0}, 0, 2, 262 },
|
|
{ GAS_ILLEGAL, 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0xF3, 2, {0x0F, 0x7E, 0}, 0, 2, 88 },
|
|
{ GAS_ILLEGAL, 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0xF3, 2, {0x0F, 0x7E, 0}, 0, 2, 298 },
|
|
{ GAS_ILLEGAL, ONLY_64, CPU_SSE2, 0, 0, {0, 0, 0}, 64, 0, 0x66, 2, {0x0F, 0x6E, 0}, 0, 2, 266 },
|
|
{ GAS_ILLEGAL, 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0xD6, 0}, 0, 2, 300 },
|
|
{ GAS_ILLEGAL, ONLY_64, CPU_SSE2, 0, 0, {0, 0, 0}, 64, 0, 0x66, 2, {0x0F, 0x7E, 0}, 0, 2, 183 }
|
|
};
|
|
|
|
static const x86_insn_info mmxsse2_insn[] = {
|
|
{ 0, 0, CPU_MMX, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 213 },
|
|
{ 0, 0, CPU_SSE2, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0x00, 0}, 0, 2, 186 }
|
|
};
|
|
|
|
static const x86_insn_info pshift_insn[] = {
|
|
{ 0, 0, CPU_MMX, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 213 },
|
|
{ 0, 0, CPU_MMX, 0, 0, {MOD_Gap, MOD_Op1Add, MOD_SpAdd}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 163 },
|
|
{ 0, 0, CPU_SSE2, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0x00, 0}, 0, 2, 186 },
|
|
{ 0, 0, CPU_SSE2, 0, 0, {MOD_Gap, MOD_Op1Add, MOD_SpAdd}, 0, 0, 0x66, 2, {0x0F, 0x00, 0}, 0, 2, 2 }
|
|
};
|
|
|
|
static const x86_insn_info vpshift_insn[] = {
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0xC1, 2, {0x0F, 0x00, 0}, 0, 2, 159 },
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Gap, MOD_Op1Add, MOD_SpAdd}, 0, 0, 0xC1, 2, {0x0F, 0x00, 0}, 0, 2, 446 },
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0xC1, 2, {0x0F, 0x00, 0}, 0, 3, 52 },
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Gap, MOD_Op1Add, MOD_SpAdd}, 0, 0, 0xC1, 2, {0x0F, 0x00, 0}, 0, 3, 1 }
|
|
};
|
|
|
|
static const x86_insn_info xmm_xmm128_256_insn[] = {
|
|
{ 0, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 159 },
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 3, 52 },
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 2, {0x0F, 0x00, 0}, 0, 3, 8 }
|
|
};
|
|
|
|
static const x86_insn_info xmm_xmm128_insn[] = {
|
|
{ 0, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 159 },
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 3, 52 }
|
|
};
|
|
|
|
static const x86_insn_info cvt_rx_xmm32_insn[] = {
|
|
{ SUF_L, 0, CPU_386, CPU_SSE, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 165 },
|
|
{ SUF_L, 0, CPU_386, CPU_SSE, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 324 },
|
|
{ SUF_Q, ONLY_64, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 64, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 171 },
|
|
{ SUF_Q, ONLY_64, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 64, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 326 }
|
|
};
|
|
|
|
static const x86_insn_info cvt_mm_xmm64_insn[] = {
|
|
{ 0, 0, CPU_SSE, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 280 },
|
|
{ 0, 0, CPU_SSE, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 282 }
|
|
};
|
|
|
|
static const x86_insn_info cvt_xmm_mm_ps_insn[] = {
|
|
{ 0, 0, CPU_SSE, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 298 }
|
|
};
|
|
|
|
static const x86_insn_info cvt_xmm_rmx_insn[] = {
|
|
{ SUF_L, 0, CPU_386, CPU_SSE, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 566 },
|
|
{ SUF_L, NOT_64, CPU_386, CPU_SSE, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 150 },
|
|
{ SUF_Q, ONLY_64, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 64, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 568 },
|
|
{ SUF_L, ONLY_AVX|NOT_64, CPU_386, CPU_AVX, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 3, 24 },
|
|
{ SUF_L, ONLY_AVX, CPU_386, CPU_AVX, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 3, 246 },
|
|
{ SUF_Q, ONLY_64|ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 64, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 3, 249 }
|
|
};
|
|
|
|
static const x86_insn_info xmm_xmm32_insn[] = {
|
|
{ 0, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 108 },
|
|
{ 0, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 156 },
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 3, 0 },
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 3, 48 }
|
|
};
|
|
|
|
static const x86_insn_info ssecmp_128_insn[] = {
|
|
{ 0, 0, CPU_SSE, 0, 0, {MOD_Imm8, MOD_PreAdd, MOD_SetVEX}, 0, 0, 0, 2, {0x0F, 0xC2, 0}, 0, 2, 159 },
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Imm8, MOD_PreAdd, 0}, 0, 0, 0xC0, 2, {0x0F, 0xC2, 0}, 0, 3, 52 },
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Imm8, MOD_PreAdd, 0}, 0, 0, 0xC4, 2, {0x0F, 0xC2, 0}, 0, 3, 8 }
|
|
};
|
|
|
|
static const x86_insn_info ssecmp_32_insn[] = {
|
|
{ 0, 0, CPU_SSE, 0, 0, {MOD_Imm8, MOD_PreAdd, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0xC2, 0}, 0, 2, 108 },
|
|
{ 0, 0, CPU_SSE, 0, 0, {MOD_Imm8, MOD_PreAdd, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0xC2, 0}, 0, 2, 156 },
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Imm8, MOD_PreAdd, 0}, 0, 0, 0xC0, 2, {0x0F, 0xC2, 0}, 0, 3, 0 },
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Imm8, MOD_PreAdd, 0}, 0, 0, 0xC0, 2, {0x0F, 0xC2, 0}, 0, 3, 48 }
|
|
};
|
|
|
|
static const x86_insn_info xmm_xmm128_imm_insn[] = {
|
|
{ 0, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 3, 186 }
|
|
};
|
|
|
|
static const x86_insn_info xmm_xmm128_imm_256_insn[] = {
|
|
{ 0, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 3, 159 },
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 4, 52 },
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 2, {0x0F, 0x00, 0}, 0, 4, 8 }
|
|
};
|
|
|
|
static const x86_insn_info xmm_xmm32_imm_insn[] = {
|
|
{ 0, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 3, 108 },
|
|
{ 0, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 3, 156 },
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 4, 0 },
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 4, 48 }
|
|
};
|
|
|
|
static const x86_insn_info ldstmxcsr_insn[] = {
|
|
{ 0, 0, CPU_SSE, 0, 0, {MOD_SpAdd, MOD_SetVEX, 0}, 0, 0, 0, 2, {0x0F, 0xAE, 0}, 0, 1, 50 }
|
|
};
|
|
|
|
static const x86_insn_info maskmovq_insn[] = {
|
|
{ 0, 0, CPU_MMX, CPU_P3, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xF7, 0}, 0, 2, 560 }
|
|
};
|
|
|
|
static const x86_insn_info movau_insn[] = {
|
|
{ 0, NOT_AVX, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 186 },
|
|
{ 0, NOT_AVX, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_Op1Add}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 428 },
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 2, 186 },
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_Op1Add}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 2, 428 },
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 2, {0x0F, 0x00, 0}, 0, 2, 201 },
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_Op1Add}, 0, 0, 0xC4, 2, {0x0F, 0x00, 0}, 0, 2, 430 }
|
|
};
|
|
|
|
static const x86_insn_info movhllhps_insn[] = {
|
|
{ 0, 0, CPU_SSE, 0, 0, {MOD_Op1Add, MOD_SetVEX, 0}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 108 },
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 3, 0 }
|
|
};
|
|
|
|
static const x86_insn_info movhlp_insn[] = {
|
|
{ 0, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 111 },
|
|
{ 0, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x01, 0}, 0, 2, 39 },
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 3, 4 }
|
|
};
|
|
|
|
static const x86_insn_info movmsk_insn[] = {
|
|
{ SUF_L, 0, CPU_386, CPU_SSE, 0, {MOD_PreAdd, MOD_SetVEX, 0}, 0, 0, 0x00, 2, {0x0F, 0x50, 0}, 0, 2, 165 },
|
|
{ SUF_Q, ONLY_64, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_SetVEX, 0}, 64, 0, 0x00, 2, {0x0F, 0x50, 0}, 0, 2, 171 },
|
|
{ SUF_L, ONLY_AVX, CPU_386, CPU_AVX, 0, {MOD_PreAdd, 0, 0}, 0, 0, 0xC4, 2, {0x0F, 0x50, 0}, 0, 2, 284 },
|
|
{ SUF_Q, ONLY_64|ONLY_AVX, CPU_SSE, 0, 0, {MOD_PreAdd, 0, 0}, 64, 0, 0xC4, 2, {0x0F, 0x50, 0}, 0, 2, 286 }
|
|
};
|
|
|
|
static const x86_insn_info movnt_insn[] = {
|
|
{ 0, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 520 },
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 2, {0x0F, 0x00, 0}, 0, 2, 522 }
|
|
};
|
|
|
|
static const x86_insn_info movntq_insn[] = {
|
|
{ 0, 0, CPU_SSE, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xE7, 0}, 0, 2, 328 }
|
|
};
|
|
|
|
static const x86_insn_info movss_insn[] = {
|
|
{ 0, 0, CPU_SSE, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0xF3, 2, {0x0F, 0x10, 0}, 0, 2, 108 },
|
|
{ 0, 0, CPU_SSE, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0xF3, 2, {0x0F, 0x10, 0}, 0, 2, 301 },
|
|
{ 0, 0, CPU_SSE, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0xF3, 2, {0x0F, 0x11, 0}, 0, 2, 518 },
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC2, 2, {0x0F, 0x10, 0}, 0, 3, 0 }
|
|
};
|
|
|
|
static const x86_insn_info pextrw_insn[] = {
|
|
{ SUF_L, NOT_AVX, CPU_MMX, CPU_P3, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xC5, 0}, 0, 3, 162 },
|
|
{ SUF_L, 0, CPU_386, CPU_SSE2, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0xC5, 0}, 0, 3, 165 },
|
|
{ SUF_Q, ONLY_64|NOT_AVX, CPU_MMX, CPU_P3, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0xC5, 0}, 0, 3, 168 },
|
|
{ SUF_Q, ONLY_64, CPU_SSE2, 0, 0, {MOD_SetVEX, 0, 0}, 64, 0, 0x66, 2, {0x0F, 0xC5, 0}, 0, 3, 171 },
|
|
{ 0, 0, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x15}, 0, 3, 174 },
|
|
{ 0, 0, CPU_386, CPU_SSE41, 0, {MOD_SetVEX, 0, 0}, 32, 0, 0x66, 3, {0x0F, 0x3A, 0x15}, 0, 3, 177 },
|
|
{ 0, ONLY_64, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 64, 0, 0x66, 3, {0x0F, 0x3A, 0x15}, 0, 3, 180 }
|
|
};
|
|
|
|
static const x86_insn_info pinsrw_insn[] = {
|
|
{ SUF_L, NOT_AVX, CPU_MMX, CPU_P3, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xC4, 0}, 0, 3, 132 },
|
|
{ SUF_Q, ONLY_64|NOT_AVX, CPU_MMX, CPU_P3, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0xC4, 0}, 0, 3, 135 },
|
|
{ SUF_L, NOT_AVX, CPU_MMX, CPU_P3, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xC4, 0}, 0, 3, 138 },
|
|
{ SUF_L, 0, CPU_386, CPU_SSE2, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0xC4, 0}, 0, 3, 141 },
|
|
{ SUF_Q, ONLY_64, CPU_SSE2, 0, 0, {MOD_SetVEX, 0, 0}, 64, 0, 0x66, 2, {0x0F, 0xC4, 0}, 0, 3, 144 },
|
|
{ SUF_L, 0, CPU_SSE2, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0xC4, 0}, 0, 3, 147 },
|
|
{ SUF_L, ONLY_AVX, CPU_386, CPU_AVX, 0, {0, 0, 0}, 0, 0, 0xC1, 2, {0x0F, 0xC4, 0}, 0, 4, 12 },
|
|
{ SUF_Q, ONLY_64|ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 64, 0, 0xC1, 2, {0x0F, 0xC4, 0}, 0, 4, 16 },
|
|
{ SUF_L, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC1, 2, {0x0F, 0xC4, 0}, 0, 4, 20 }
|
|
};
|
|
|
|
static const x86_insn_info pmovmskb_insn[] = {
|
|
{ SUF_L, NOT_AVX, CPU_MMX, CPU_P3, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xD7, 0}, 0, 2, 162 },
|
|
{ SUF_L, 0, CPU_386, CPU_SSE2, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0xD7, 0}, 0, 2, 165 },
|
|
{ SUF_Q, ONLY_64|NOT_AVX, CPU_MMX, CPU_P3, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0xD7, 0}, 0, 2, 168 },
|
|
{ SUF_Q, ONLY_64, CPU_SSE2, 0, 0, {MOD_SetVEX, 0, 0}, 64, 0, 0x66, 2, {0x0F, 0xD7, 0}, 0, 2, 171 }
|
|
};
|
|
|
|
static const x86_insn_info pshufw_insn[] = {
|
|
{ 0, 0, CPU_MMX, CPU_P3, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x70, 0}, 0, 3, 213 }
|
|
};
|
|
|
|
static const x86_insn_info xmm_xmm64_insn[] = {
|
|
{ 0, 0, CPU_SSE2, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 108 },
|
|
{ 0, 0, CPU_SSE2, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 111 },
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 3, 0 },
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 3, 4 }
|
|
};
|
|
|
|
static const x86_insn_info ssecmp_64_insn[] = {
|
|
{ 0, 0, CPU_SSE2, 0, 0, {MOD_Imm8, MOD_PreAdd, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0xC2, 0}, 0, 2, 108 },
|
|
{ 0, 0, CPU_SSE2, 0, 0, {MOD_Imm8, MOD_PreAdd, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0xC2, 0}, 0, 2, 111 },
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Imm8, MOD_PreAdd, 0}, 0, 0, 0xC0, 2, {0x0F, 0xC2, 0}, 0, 3, 0 },
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Imm8, MOD_PreAdd, 0}, 0, 0, 0xC0, 2, {0x0F, 0xC2, 0}, 0, 3, 4 }
|
|
};
|
|
|
|
static const x86_insn_info cvt_rx_xmm64_insn[] = {
|
|
{ SUF_L, 0, CPU_386, CPU_SSE2, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 165 },
|
|
{ SUF_L, 0, CPU_386, CPU_SSE2, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 303 },
|
|
{ SUF_Q, ONLY_64, CPU_SSE2, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 64, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 171 },
|
|
{ SUF_Q, ONLY_64, CPU_SSE2, 0, 0, {MOD_PreAdd, MOD_Op1Add, MOD_SetVEX}, 64, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 416 }
|
|
};
|
|
|
|
static const x86_insn_info cvt_mm_xmm_insn[] = {
|
|
{ 0, 0, CPU_SSE2, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 544 }
|
|
};
|
|
|
|
static const x86_insn_info cvt_xmm_mm_ss_insn[] = {
|
|
{ 0, 0, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 2, 298 }
|
|
};
|
|
|
|
static const x86_insn_info vmxmemrd_insn[] = {
|
|
{ SUF_L, NOT_64, CPU_P4, 0, 0, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0x78, 0}, 0, 2, 234 },
|
|
{ SUF_Q, ONLY_64, CPU_P4, 0, 0, {0, 0, 0}, 64, 64, 0, 2, {0x0F, 0x78, 0}, 0, 2, 240 }
|
|
};
|
|
|
|
static const x86_insn_info vmxmemwr_insn[] = {
|
|
{ SUF_L, NOT_64, CPU_P4, 0, 0, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0x79, 0}, 0, 2, 117 },
|
|
{ SUF_Q, ONLY_64, CPU_P4, 0, 0, {0, 0, 0}, 64, 64, 0, 2, {0x0F, 0x79, 0}, 0, 2, 120 }
|
|
};
|
|
|
|
static const x86_insn_info vmxtwobytemem_insn[] = {
|
|
{ 0, 0, CPU_P4, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 2, {0x0F, 0xC7, 0}, 0, 1, 6 }
|
|
};
|
|
|
|
static const x86_insn_info vmxthreebytemem_insn[] = {
|
|
{ 0, 0, CPU_P4, 0, 0, {MOD_PreAdd, 0, 0}, 0, 0, 0x00, 2, {0x0F, 0xC7, 0}, 6, 1, 6 }
|
|
};
|
|
|
|
static const x86_insn_info maskmovdqu_insn[] = {
|
|
{ 0, 0, CPU_SSE2, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0xF7, 0}, 0, 2, 88 }
|
|
};
|
|
|
|
static const x86_insn_info movdq2q_insn[] = {
|
|
{ 0, 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0xF2, 2, {0x0F, 0xD6, 0}, 0, 2, 280 }
|
|
};
|
|
|
|
static const x86_insn_info movq2dq_insn[] = {
|
|
{ 0, 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0xF3, 2, {0x0F, 0xD6, 0}, 0, 2, 410 }
|
|
};
|
|
|
|
static const x86_insn_info pslrldq_insn[] = {
|
|
{ 0, 0, CPU_SSE2, 0, 0, {MOD_SpAdd, MOD_SetVEX, 0}, 0, 0, 0x66, 2, {0x0F, 0x73, 0}, 0, 2, 446 },
|
|
{ 0, 0, CPU_SSE2, 0, 0, {MOD_SpAdd, MOD_SetVEX, 0}, 0, 0, 0x66, 2, {0x0F, 0x73, 0}, 0, 3, 1 }
|
|
};
|
|
|
|
static const x86_insn_info lddqu_insn[] = {
|
|
{ 0, 0, CPU_SSE3, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0xF2, 2, {0x0F, 0xF0, 0}, 0, 2, 516 },
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC7, 2, {0x0F, 0xF0, 0}, 0, 2, 558 }
|
|
};
|
|
|
|
static const x86_insn_info ssse3_insn[] = {
|
|
{ 0, NOT_AVX, CPU_SSSE3, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 3, {0x0F, 0x38, 0x00}, 0, 2, 213 },
|
|
{ 0, 0, CPU_SSSE3, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x38, 0x00}, 0, 2, 159 },
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x00}, 0, 3, 52 }
|
|
};
|
|
|
|
static const x86_insn_info ssse3imm_insn[] = {
|
|
{ 0, 0, CPU_SSSE3, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 3, {0x0F, 0x3A, 0x00}, 0, 3, 213 },
|
|
{ 0, 0, CPU_SSSE3, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x00}, 0, 3, 186 }
|
|
};
|
|
|
|
static const x86_insn_info sse4_insn[] = {
|
|
{ 0, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x38, 0x00}, 0, 2, 186 },
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x00}, 0, 2, 201 }
|
|
};
|
|
|
|
static const x86_insn_info sse4imm_256_insn[] = {
|
|
{ 0, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x00}, 0, 3, 159 },
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 52 },
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x3A, 0x00}, 0, 4, 8 }
|
|
};
|
|
|
|
static const x86_insn_info sse4imm_insn[] = {
|
|
{ 0, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x00}, 0, 3, 159 },
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 52 }
|
|
};
|
|
|
|
static const x86_insn_info sse4m32imm_insn[] = {
|
|
{ 0, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x00}, 0, 3, 108 },
|
|
{ 0, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x00}, 0, 3, 156 },
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 0 },
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 48 }
|
|
};
|
|
|
|
static const x86_insn_info sse4m64imm_insn[] = {
|
|
{ 0, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x00}, 0, 3, 108 },
|
|
{ 0, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x00}, 0, 3, 111 },
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 0 },
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 4 }
|
|
};
|
|
|
|
static const x86_insn_info sse4xmm0_insn[] = {
|
|
{ 0, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x38, 0x00}, 0, 2, 186 },
|
|
{ 0, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x38, 0x00}, 0, 3, 210 }
|
|
};
|
|
|
|
static const x86_insn_info avx_sse4xmm0_insn[] = {
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 60 },
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x3A, 0x00}, 0, 4, 64 }
|
|
};
|
|
|
|
static const x86_insn_info avx_sse4xmm0_128_insn[] = {
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 60 }
|
|
};
|
|
|
|
static const x86_insn_info crc32_insn[] = {
|
|
{ SUF_B, 0, CPU_386, CPU_SSE42, 0, {0, 0, 0}, 0, 0, 0xF2, 3, {0x0F, 0x38, 0xF0}, 0, 2, 470 },
|
|
{ SUF_W, 0, CPU_386, CPU_SSE42, 0, {0, 0, 0}, 16, 0, 0xF2, 3, {0x0F, 0x38, 0xF1}, 0, 2, 472 },
|
|
{ SUF_L, 0, CPU_386, CPU_SSE42, 0, {0, 0, 0}, 32, 0, 0xF2, 3, {0x0F, 0x38, 0xF1}, 0, 2, 117 },
|
|
{ SUF_B, ONLY_64, CPU_SSE42, 0, 0, {0, 0, 0}, 64, 0, 0xF2, 3, {0x0F, 0x38, 0xF0}, 0, 2, 474 },
|
|
{ SUF_Q, ONLY_64, CPU_SSE42, 0, 0, {0, 0, 0}, 64, 0, 0xF2, 3, {0x0F, 0x38, 0xF1}, 0, 2, 120 }
|
|
};
|
|
|
|
static const x86_insn_info extractps_insn[] = {
|
|
{ 0, 0, CPU_386, CPU_SSE41, 0, {MOD_SetVEX, 0, 0}, 32, 0, 0x66, 3, {0x0F, 0x3A, 0x17}, 0, 3, 189 },
|
|
{ 0, ONLY_64, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 64, 0, 0x66, 3, {0x0F, 0x3A, 0x17}, 0, 3, 180 }
|
|
};
|
|
|
|
static const x86_insn_info insertps_insn[] = {
|
|
{ 0, 0, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x21}, 0, 3, 156 },
|
|
{ 0, 0, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x21}, 0, 3, 108 },
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x21}, 0, 4, 48 },
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x21}, 0, 4, 0 }
|
|
};
|
|
|
|
static const x86_insn_info movntdqa_insn[] = {
|
|
{ 0, 0, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x38, 0x2A}, 0, 2, 516 }
|
|
};
|
|
|
|
static const x86_insn_info sse4pcmpstr_insn[] = {
|
|
{ 0, 0, CPU_SSE42, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x00}, 0, 3, 186 }
|
|
};
|
|
|
|
static const x86_insn_info pextrb_insn[] = {
|
|
{ 0, 0, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x14}, 0, 3, 204 },
|
|
{ 0, 0, CPU_386, CPU_SSE41, 0, {MOD_SetVEX, 0, 0}, 32, 0, 0x66, 3, {0x0F, 0x3A, 0x14}, 0, 3, 177 },
|
|
{ 0, ONLY_64, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 64, 0, 0x66, 3, {0x0F, 0x3A, 0x14}, 0, 3, 180 }
|
|
};
|
|
|
|
static const x86_insn_info pextrd_insn[] = {
|
|
{ 0, 0, CPU_386, CPU_SSE41, 0, {MOD_SetVEX, 0, 0}, 32, 0, 0x66, 3, {0x0F, 0x3A, 0x16}, 0, 3, 189 }
|
|
};
|
|
|
|
static const x86_insn_info pextrq_insn[] = {
|
|
{ 0, ONLY_64, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 64, 0, 0x66, 3, {0x0F, 0x3A, 0x16}, 0, 3, 183 }
|
|
};
|
|
|
|
static const x86_insn_info pinsrb_insn[] = {
|
|
{ 0, 0, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x20}, 0, 3, 153 },
|
|
{ 0, 0, CPU_386, CPU_SSE41, 0, {MOD_SetVEX, 0, 0}, 32, 0, 0x66, 3, {0x0F, 0x3A, 0x20}, 0, 3, 141 },
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x20}, 0, 4, 40 },
|
|
{ 0, ONLY_AVX, CPU_386, CPU_AVX, 0, {0, 0, 0}, 32, 0, 0xC1, 3, {0x0F, 0x3A, 0x20}, 0, 4, 44 }
|
|
};
|
|
|
|
static const x86_insn_info pinsrd_insn[] = {
|
|
{ 0, 0, CPU_386, CPU_SSE41, 0, {MOD_SetVEX, 0, 0}, 32, 0, 0x66, 3, {0x0F, 0x3A, 0x22}, 0, 3, 150 },
|
|
{ 0, ONLY_AVX, CPU_386, CPU_AVX, 0, {0, 0, 0}, 32, 0, 0xC1, 3, {0x0F, 0x3A, 0x22}, 0, 4, 24 }
|
|
};
|
|
|
|
static const x86_insn_info pinsrq_insn[] = {
|
|
{ 0, ONLY_64, CPU_SSE41, 0, 0, {MOD_SetVEX, 0, 0}, 64, 0, 0x66, 3, {0x0F, 0x3A, 0x22}, 0, 3, 225 },
|
|
{ 0, ONLY_64|ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 64, 0, 0xC1, 3, {0x0F, 0x3A, 0x22}, 0, 4, 76 }
|
|
};
|
|
|
|
static const x86_insn_info sse4m16_insn[] = {
|
|
{ 0, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x38, 0x00}, 0, 2, 412 },
|
|
{ 0, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x38, 0x00}, 0, 2, 88 }
|
|
};
|
|
|
|
static const x86_insn_info sse4m32_insn[] = {
|
|
{ 0, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x38, 0x00}, 0, 2, 301 },
|
|
{ 0, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x38, 0x00}, 0, 2, 88 }
|
|
};
|
|
|
|
static const x86_insn_info sse4m64_insn[] = {
|
|
{ 0, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x38, 0x00}, 0, 2, 216 },
|
|
{ 0, 0, CPU_SSE41, 0, 0, {MOD_Op2Add, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x38, 0x00}, 0, 2, 88 }
|
|
};
|
|
|
|
static const x86_insn_info cnt_insn[] = {
|
|
{ SUF_W, 0, 0, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0xF3, 2, {0x0F, 0x00, 0}, 0, 2, 114 },
|
|
{ SUF_L, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0xF3, 2, {0x0F, 0x00, 0}, 0, 2, 117 },
|
|
{ SUF_Q, ONLY_64, 0, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0xF3, 2, {0x0F, 0x00, 0}, 0, 2, 120 }
|
|
};
|
|
|
|
static const x86_insn_info vmovd_insn[] = {
|
|
{ 0, ONLY_AVX, CPU_386, CPU_AVX, 0, {0, 0, 0}, 0, 0, 0xC1, 2, {0x0F, 0x6E, 0}, 0, 2, 264 },
|
|
{ 0, ONLY_AVX, CPU_386, CPU_AVX, 0, {0, 0, 0}, 0, 0, 0xC1, 2, {0x0F, 0x7E, 0}, 0, 2, 189 }
|
|
};
|
|
|
|
static const x86_insn_info vmovq_insn[] = {
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC2, 2, {0x0F, 0x7E, 0}, 0, 2, 88 },
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC2, 2, {0x0F, 0x7E, 0}, 0, 2, 216 },
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC1, 2, {0x0F, 0xD6, 0}, 0, 2, 39 },
|
|
{ 0, ONLY_64|ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 64, 0, 0xC1, 2, {0x0F, 0x6E, 0}, 0, 2, 266 },
|
|
{ 0, ONLY_64|ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 64, 0, 0xC1, 2, {0x0F, 0x7E, 0}, 0, 2, 183 }
|
|
};
|
|
|
|
static const x86_insn_info avx_xmm_xmm128_insn[] = {
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 2, 186 },
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 2, {0x0F, 0x00, 0}, 0, 2, 201 }
|
|
};
|
|
|
|
static const x86_insn_info avx_sse4imm_insn[] = {
|
|
{ 0, ONLY_AVX, CPU_SSE41, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 3, 186 },
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 3, 186 },
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x3A, 0x00}, 0, 3, 201 }
|
|
};
|
|
|
|
static const x86_insn_info vmovddup_insn[] = {
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 2, 88 },
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 2, 216 },
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 2, {0x0F, 0x00, 0}, 0, 2, 201 }
|
|
};
|
|
|
|
static const x86_insn_info avx_xmm_xmm64_insn[] = {
|
|
{ 0, ONLY_AVX, CPU_SSE2, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 2, 88 },
|
|
{ 0, ONLY_AVX, CPU_SSE2, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 2, 216 }
|
|
};
|
|
|
|
static const x86_insn_info avx_xmm_xmm32_insn[] = {
|
|
{ 0, ONLY_AVX, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 2, 88 },
|
|
{ 0, ONLY_AVX, CPU_SSE, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 2, 301 }
|
|
};
|
|
|
|
static const x86_insn_info avx_cvt_xmm64_insn[] = {
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 2, 88 },
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 2, 216 },
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 2, {0x0F, 0x00, 0}, 0, 2, 222 }
|
|
};
|
|
|
|
static const x86_insn_info avx_ssse3_2op_insn[] = {
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x00}, 0, 2, 186 }
|
|
};
|
|
|
|
static const x86_insn_info avx_cvt_xmm128_x_insn[] = {
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 2, 186 }
|
|
};
|
|
|
|
static const x86_insn_info avx_cvt_xmm128_y_insn[] = {
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 2, {0x0F, 0x00, 0}, 0, 2, 429 }
|
|
};
|
|
|
|
static const x86_insn_info avx_cvt_xmm128_insn[] = {
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC0, 2, {0x0F, 0x00, 0}, 0, 2, 528 },
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_PreAdd, MOD_Op1Add, 0}, 0, 0, 0xC4, 2, {0x0F, 0x00, 0}, 0, 2, 530 }
|
|
};
|
|
|
|
static const x86_insn_info vbroadcastss_insn[] = {
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x18}, 0, 2, 301 },
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x18}, 0, 2, 432 }
|
|
};
|
|
|
|
static const x86_insn_info vbroadcastsd_insn[] = {
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x19}, 0, 2, 426 }
|
|
};
|
|
|
|
static const x86_insn_info vbroadcastf128_insn[] = {
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x1A}, 0, 2, 548 }
|
|
};
|
|
|
|
static const x86_insn_info vextractf128_insn[] = {
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x3A, 0x19}, 0, 3, 198 }
|
|
};
|
|
|
|
static const x86_insn_info vinsertf128_insn[] = {
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x3A, 0x18}, 0, 4, 56 }
|
|
};
|
|
|
|
static const x86_insn_info vzero_insn[] = {
|
|
{ 0, 0, CPU_AVX, 0, 0, {MOD_SetVEX, 0, 0}, 0, 0, 0, 2, {0x0F, 0x77, 0}, 0, 0, 0 }
|
|
};
|
|
|
|
static const x86_insn_info vmaskmov_insn[] = {
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x00}, 0, 3, 52 },
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x00}, 0, 3, 8 },
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x02}, 0, 3, 94 },
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x02}, 0, 3, 102 }
|
|
};
|
|
|
|
static const x86_insn_info vpermil_insn[] = {
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x08}, 0, 3, 52 },
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x08}, 0, 3, 8 },
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 3, 186 },
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x3A, 0x00}, 0, 3, 201 }
|
|
};
|
|
|
|
static const x86_insn_info vperm2f128_insn[] = {
|
|
{ 0, ONLY_AVX, CPU_AVX, 0, 0, {0, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x3A, 0x06}, 0, 4, 8 }
|
|
};
|
|
|
|
static const x86_insn_info vfma_ps_insn[] = {
|
|
{ 0, ONLY_AVX, CPU_FMA, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x00}, 0, 3, 52 },
|
|
{ 0, ONLY_AVX, CPU_FMA, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x38, 0x00}, 0, 3, 8 }
|
|
};
|
|
|
|
static const x86_insn_info vfma_pd_insn[] = {
|
|
{ 0, ONLY_AVX, CPU_FMA, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC9, 3, {0x0F, 0x38, 0x00}, 0, 3, 52 },
|
|
{ 0, ONLY_AVX, CPU_FMA, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xCD, 3, {0x0F, 0x38, 0x00}, 0, 3, 8 }
|
|
};
|
|
|
|
static const x86_insn_info vfma_ss_insn[] = {
|
|
{ 0, ONLY_AVX, CPU_FMA, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x00}, 0, 3, 0 },
|
|
{ 0, ONLY_AVX, CPU_FMA, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x38, 0x00}, 0, 3, 48 }
|
|
};
|
|
|
|
static const x86_insn_info vfma_sd_insn[] = {
|
|
{ 0, ONLY_AVX, CPU_FMA, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC9, 3, {0x0F, 0x38, 0x00}, 0, 3, 0 },
|
|
{ 0, ONLY_AVX, CPU_FMA, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC9, 3, {0x0F, 0x38, 0x00}, 0, 3, 4 }
|
|
};
|
|
|
|
static const x86_insn_info aes_insn[] = {
|
|
{ 0, 0, CPU_AES, 0, 0, {MOD_Op1Add, MOD_Op2Add, MOD_SetVEX}, 0, 0, 0x66, 3, {0x0F, 0x00, 0x00}, 0, 2, 159 },
|
|
{ 0, ONLY_AVX, CPU_AES, CPU_AVX, 0, {MOD_Op1Add, MOD_Op2Add, 0}, 0, 0, 0xC1, 3, {0x0F, 0x00, 0x00}, 0, 3, 52 }
|
|
};
|
|
|
|
static const x86_insn_info aesimc_insn[] = {
|
|
{ 0, 0, CPU_AES, 0, 0, {MOD_Op1Add, MOD_Op2Add, MOD_SetVEX}, 0, 0, 0x66, 3, {0x0F, 0x00, 0x00}, 0, 2, 159 }
|
|
};
|
|
|
|
static const x86_insn_info aes_imm_insn[] = {
|
|
{ 0, 0, CPU_AES, 0, 0, {MOD_Op1Add, MOD_Op2Add, MOD_SetVEX}, 0, 0, 0x66, 3, {0x0F, 0x00, 0x00}, 0, 3, 186 }
|
|
};
|
|
|
|
static const x86_insn_info pclmulqdq_insn[] = {
|
|
{ 0, 0, CPU_CLMUL, 0, 0, {MOD_Op1Add, MOD_Op2Add, MOD_SetVEX}, 0, 0, 0x66, 3, {0x0F, 0x00, 0x00}, 0, 3, 159 },
|
|
{ 0, ONLY_AVX, CPU_AVX, CPU_CLMUL, 0, {MOD_Op1Add, MOD_Op2Add, 0}, 0, 0, 0xC1, 3, {0x0F, 0x00, 0x00}, 0, 4, 52 }
|
|
};
|
|
|
|
static const x86_insn_info pclmulqdq_fixed_insn[] = {
|
|
{ 0, 0, CPU_CLMUL, 0, 0, {MOD_Imm8, MOD_SetVEX, 0}, 0, 0, 0x66, 3, {0x0F, 0x3A, 0x44}, 0, 2, 159 },
|
|
{ 0, ONLY_AVX, CPU_AVX, CPU_CLMUL, 0, {MOD_Imm8, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x44}, 0, 3, 52 }
|
|
};
|
|
|
|
static const x86_insn_info extrq_insn[] = {
|
|
{ 0, 0, CPU_SSE4a, 0, 0, {0, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0x78, 0}, 0, 3, 89 },
|
|
{ 0, 0, CPU_SSE4a, 0, 0, {0, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0x79, 0}, 0, 2, 88 }
|
|
};
|
|
|
|
static const x86_insn_info insertq_insn[] = {
|
|
{ 0, 0, CPU_SSE4a, 0, 0, {0, 0, 0}, 0, 0, 0xF2, 2, {0x0F, 0x78, 0}, 0, 4, 88 },
|
|
{ 0, 0, CPU_SSE4a, 0, 0, {0, 0, 0}, 0, 0, 0xF2, 2, {0x0F, 0x79, 0}, 0, 2, 88 }
|
|
};
|
|
|
|
static const x86_insn_info movntsd_insn[] = {
|
|
{ 0, 0, CPU_SSE4a, 0, 0, {0, 0, 0}, 0, 0, 0xF2, 2, {0x0F, 0x2B, 0}, 0, 2, 39 }
|
|
};
|
|
|
|
static const x86_insn_info movntss_insn[] = {
|
|
{ 0, 0, CPU_SSE4a, 0, 0, {0, 0, 0}, 0, 0, 0xF3, 2, {0x0F, 0x2B, 0}, 0, 2, 518 }
|
|
};
|
|
|
|
static const x86_insn_info vcvtph2ps_insn[] = {
|
|
{ 0, 0, CPU_CVT16, 0, 0, {0, 0, 0}, 0, 0, 0x80, 2, {0x08, 0xA0, 0}, 0, 3, 216 },
|
|
{ 0, 0, CPU_CVT16, 0, 0, {0, 0, 0}, 0, 0, 0x80, 2, {0x08, 0xA0, 0}, 0, 3, 219 },
|
|
{ 0, 0, CPU_CVT16, 0, 0, {0, 0, 0}, 0, 0, 0x84, 2, {0x08, 0xA0, 0}, 0, 3, 222 }
|
|
};
|
|
|
|
static const x86_insn_info vcvtps2ph_insn[] = {
|
|
{ 0, 0, CPU_CVT16, 0, 0, {0, 0, 0}, 0, 0, 0x80, 2, {0x08, 0xA1, 0}, 0, 3, 192 },
|
|
{ 0, 0, CPU_CVT16, 0, 0, {0, 0, 0}, 0, 0, 0x80, 2, {0x08, 0xA1, 0}, 0, 3, 195 },
|
|
{ 0, 0, CPU_CVT16, 0, 0, {0, 0, 0}, 0, 0, 0x84, 2, {0x08, 0xA1, 0}, 0, 3, 198 }
|
|
};
|
|
|
|
static const x86_insn_info vfrc_pdps_insn[] = {
|
|
{ 0, 0, CPU_XOP, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x80, 2, {0x09, 0x80, 0}, 0, 2, 186 },
|
|
{ 0, 0, CPU_XOP, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x84, 2, {0x09, 0x80, 0}, 0, 2, 201 }
|
|
};
|
|
|
|
static const x86_insn_info vfrczsd_insn[] = {
|
|
{ 0, 0, CPU_XOP, 0, 0, {0, 0, 0}, 0, 0, 0x80, 2, {0x09, 0x83, 0}, 0, 2, 88 },
|
|
{ 0, 0, CPU_XOP, 0, 0, {0, 0, 0}, 0, 0, 0x80, 2, {0x09, 0x83, 0}, 0, 2, 216 }
|
|
};
|
|
|
|
static const x86_insn_info vfrczss_insn[] = {
|
|
{ 0, 0, CPU_XOP, 0, 0, {0, 0, 0}, 0, 0, 0x80, 2, {0x09, 0x82, 0}, 0, 2, 88 },
|
|
{ 0, 0, CPU_XOP, 0, 0, {0, 0, 0}, 0, 0, 0x80, 2, {0x09, 0x82, 0}, 0, 2, 301 }
|
|
};
|
|
|
|
static const x86_insn_info vpcmov_insn[] = {
|
|
{ 0, 0, CPU_XOP, 0, 0, {0, 0, 0}, 0, 0, 0x80, 2, {0x08, 0xA2, 0}, 0, 4, 60 },
|
|
{ 0, 0, CPU_XOP, 0, 0, {0, 0, 0}, 0, 0, 0x88, 2, {0x08, 0xA2, 0}, 0, 4, 80 },
|
|
{ 0, 0, CPU_XOP, 0, 0, {0, 0, 0}, 0, 0, 0x84, 2, {0x08, 0xA2, 0}, 0, 4, 64 },
|
|
{ 0, 0, CPU_XOP, 0, 0, {0, 0, 0}, 0, 0, 0x8C, 2, {0x08, 0xA2, 0}, 0, 4, 84 }
|
|
};
|
|
|
|
static const x86_insn_info vpcom_insn[] = {
|
|
{ 0, 0, CPU_XOP, 0, 0, {MOD_Op1Add, MOD_Imm8, 0}, 0, 0, 0x80, 2, {0x08, 0x00, 0}, 0, 3, 52 }
|
|
};
|
|
|
|
static const x86_insn_info vpcom_imm_insn[] = {
|
|
{ 0, 0, CPU_XOP, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x80, 2, {0x08, 0x00, 0}, 0, 4, 52 }
|
|
};
|
|
|
|
static const x86_insn_info vphaddsub_insn[] = {
|
|
{ 0, 0, CPU_XOP, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x80, 2, {0x09, 0x00, 0}, 0, 2, 186 }
|
|
};
|
|
|
|
static const x86_insn_info vpma_insn[] = {
|
|
{ 0, 0, CPU_XOP, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x80, 2, {0x08, 0x00, 0}, 0, 4, 60 }
|
|
};
|
|
|
|
static const x86_insn_info vpperm_insn[] = {
|
|
{ 0, 0, CPU_XOP, 0, 0, {0, 0, 0}, 0, 0, 0x80, 2, {0x08, 0xA3, 0}, 0, 4, 60 },
|
|
{ 0, 0, CPU_XOP, 0, 0, {0, 0, 0}, 0, 0, 0x88, 2, {0x08, 0xA3, 0}, 0, 4, 80 }
|
|
};
|
|
|
|
static const x86_insn_info vprot_insn[] = {
|
|
{ 0, 0, CPU_XOP, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x80, 2, {0x09, 0x90, 0}, 0, 3, 207 },
|
|
{ 0, 0, CPU_XOP, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x88, 2, {0x09, 0x90, 0}, 0, 3, 52 },
|
|
{ 0, 0, CPU_XOP, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x80, 2, {0x08, 0xC0, 0}, 0, 3, 186 }
|
|
};
|
|
|
|
static const x86_insn_info amd_vpshift_insn[] = {
|
|
{ 0, 0, CPU_XOP, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x80, 2, {0x09, 0x00, 0}, 0, 3, 207 },
|
|
{ 0, 0, CPU_XOP, 0, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0x88, 2, {0x09, 0x00, 0}, 0, 3, 52 }
|
|
};
|
|
|
|
static const x86_insn_info fma_128_256_insn[] = {
|
|
{ 0, ONLY_AVX, CPU_FMA4, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 92 },
|
|
{ 0, ONLY_AVX, CPU_FMA4, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC9, 3, {0x0F, 0x3A, 0x00}, 0, 4, 96 },
|
|
{ 0, ONLY_AVX, CPU_FMA4, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC5, 3, {0x0F, 0x3A, 0x00}, 0, 4, 100 },
|
|
{ 0, ONLY_AVX, CPU_FMA4, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xCD, 3, {0x0F, 0x3A, 0x00}, 0, 4, 104 }
|
|
};
|
|
|
|
static const x86_insn_info fma_128_m32_insn[] = {
|
|
{ 0, ONLY_AVX, CPU_FMA4, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 28 },
|
|
{ 0, ONLY_AVX, CPU_FMA4, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 68 },
|
|
{ 0, ONLY_AVX, CPU_FMA4, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC9, 3, {0x0F, 0x3A, 0x00}, 0, 4, 72 }
|
|
};
|
|
|
|
static const x86_insn_info fma_128_m64_insn[] = {
|
|
{ 0, ONLY_AVX, CPU_FMA4, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 28 },
|
|
{ 0, ONLY_AVX, CPU_FMA4, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC1, 3, {0x0F, 0x3A, 0x00}, 0, 4, 32 },
|
|
{ 0, ONLY_AVX, CPU_FMA4, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0xC9, 3, {0x0F, 0x3A, 0x00}, 0, 4, 36 }
|
|
};
|
|
|
|
static const x86_insn_info movbe_insn[] = {
|
|
{ 0, 0, CPU_MOVBE, 0, 0, {0, 0, 0}, 16, 0, 0, 3, {0x0F, 0x38, 0xF0}, 0, 2, 414 },
|
|
{ 0, 0, CPU_MOVBE, 0, 0, {0, 0, 0}, 16, 0, 0, 3, {0x0F, 0x38, 0xF1}, 0, 2, 413 },
|
|
{ 0, 0, CPU_386, CPU_MOVBE, 0, {0, 0, 0}, 32, 0, 0, 3, {0x0F, 0x38, 0xF0}, 0, 2, 324 },
|
|
{ 0, 0, CPU_386, CPU_MOVBE, 0, {0, 0, 0}, 32, 0, 0, 3, {0x0F, 0x38, 0xF1}, 0, 2, 302 },
|
|
{ 0, ONLY_64, CPU_MOVBE, 0, 0, {0, 0, 0}, 64, 0, 0, 3, {0x0F, 0x38, 0xF0}, 0, 2, 416 },
|
|
{ 0, ONLY_64, CPU_MOVBE, 0, 0, {0, 0, 0}, 64, 0, 0, 3, {0x0F, 0x38, 0xF1}, 0, 2, 304 }
|
|
};
|
|
|
|
static const x86_insn_info now3d_insn[] = {
|
|
{ 0, 0, CPU_3DNow, 0, 0, {MOD_Imm8, 0, 0}, 0, 0, 0, 2, {0x0F, 0x0F, 0}, 0, 2, 213 }
|
|
};
|
|
|
|
static const x86_insn_info cmpxchg16b_insn[] = {
|
|
{ 0, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0xC7, 0}, 1, 1, 517 }
|
|
};
|
|
|
|
static const x86_insn_info invlpga_insn[] = {
|
|
{ 0, 0, CPU_SVM, 0, 0, {0, 0, 0}, 0, 0, 0, 3, {0x0F, 0x01, 0xDF}, 0, 0, 0 },
|
|
{ 0, 0, CPU_386, CPU_SVM, 0, {0, 0, 0}, 0, 0, 0, 3, {0x0F, 0x01, 0xDF}, 0, 2, 448 }
|
|
};
|
|
|
|
static const x86_insn_info skinit_insn[] = {
|
|
{ 0, 0, CPU_SVM, 0, 0, {0, 0, 0}, 0, 0, 0, 3, {0x0F, 0x01, 0xDE}, 0, 0, 0 },
|
|
{ 0, 0, CPU_SVM, 0, 0, {0, 0, 0}, 0, 0, 0, 3, {0x0F, 0x01, 0xDE}, 0, 1, 574 }
|
|
};
|
|
|
|
static const x86_insn_info svm_rax_insn[] = {
|
|
{ 0, 0, CPU_SVM, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 3, {0x0F, 0x01, 0x00}, 0, 0, 0 },
|
|
{ 0, 0, CPU_SVM, 0, 0, {MOD_Op2Add, 0, 0}, 0, 0, 0, 3, {0x0F, 0x01, 0x00}, 0, 1, 448 }
|
|
};
|
|
|
|
static const x86_insn_info padlock_insn[] = {
|
|
{ 0, 0, CPU_PadLock, 0, 0, {MOD_Imm8, MOD_PreAdd, MOD_Op1Add}, 0, 0, 0x00, 2, {0x0F, 0x00, 0}, 0, 0, 0 }
|
|
};
|
|
|
|
static const x86_insn_info cyrixmmx_insn[] = {
|
|
{ 0, 0, CPU_Cyrix, CPU_MMX, 0, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 213 }
|
|
};
|
|
|
|
static const x86_insn_info pmachriw_insn[] = {
|
|
{ 0, 0, CPU_Cyrix, CPU_MMX, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x5E, 0}, 0, 2, 282 }
|
|
};
|
|
|
|
static const x86_insn_info rdwrshr_insn[] = {
|
|
{ 0, 0, CPU_686, CPU_Cyrix, CPU_SMM, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0x0F, 0x36, 0}, 0, 1, 26 }
|
|
};
|
|
|
|
static const x86_insn_info rsdc_insn[] = {
|
|
{ 0, 0, CPU_486, CPU_Cyrix, CPU_SMM, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x79, 0}, 0, 2, 492 }
|
|
};
|
|
|
|
static const x86_insn_info cyrixsmm_insn[] = {
|
|
{ 0, 0, CPU_486, CPU_Cyrix, CPU_SMM, {MOD_Op1Add, 0, 0}, 0, 0, 0, 2, {0x0F, 0x00, 0}, 0, 1, 493 }
|
|
};
|
|
|
|
static const x86_insn_info svdc_insn[] = {
|
|
{ 0, 0, CPU_486, CPU_Cyrix, CPU_SMM, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x78, 0}, 0, 2, 550 }
|
|
};
|
|
|
|
static const x86_insn_info ibts_insn[] = {
|
|
{ 0, 0, CPU_386, CPU_Obs, CPU_Undoc, {0, 0, 0}, 16, 0, 0, 2, {0x0F, 0xA7, 0}, 0, 2, 228 },
|
|
{ 0, 0, CPU_386, CPU_Obs, CPU_Undoc, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0xA7, 0}, 0, 2, 234 }
|
|
};
|
|
|
|
static const x86_insn_info umov_insn[] = {
|
|
{ 0, 0, CPU_386, CPU_Undoc, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x10, 0}, 0, 2, 288 },
|
|
{ 0, 0, CPU_386, CPU_Undoc, 0, {0, 0, 0}, 16, 0, 0, 2, {0x0F, 0x11, 0}, 0, 2, 228 },
|
|
{ 0, 0, CPU_386, CPU_Undoc, 0, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0x11, 0}, 0, 2, 234 },
|
|
{ 0, 0, CPU_386, CPU_Undoc, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x12, 0}, 0, 2, 290 },
|
|
{ 0, 0, CPU_386, CPU_Undoc, 0, {0, 0, 0}, 16, 0, 0, 2, {0x0F, 0x13, 0}, 0, 2, 114 },
|
|
{ 0, 0, CPU_386, CPU_Undoc, 0, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0x13, 0}, 0, 2, 117 }
|
|
};
|
|
|
|
static const x86_insn_info xbts_insn[] = {
|
|
{ 0, 0, CPU_386, CPU_Obs, CPU_Undoc, {0, 0, 0}, 16, 0, 0, 2, {0x0F, 0xA6, 0}, 0, 2, 414 },
|
|
{ 0, 0, CPU_386, CPU_Obs, CPU_Undoc, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0xA6, 0}, 0, 2, 324 }
|
|
};
|
|
|