147 lines
5.0 KiB
Plaintext
147 lines
5.0 KiB
Plaintext
Copyright 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
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This file is part of the GNU MP Library.
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The GNU MP Library is free software; you can redistribute it and/or modify
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it under the terms of the GNU Lesser General Public License as published by
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the Free Software Foundation; either version 2.1 of the License, or (at your
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option) any later version.
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The GNU MP Library is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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License for more details.
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You should have received a copy of the GNU Lesser General Public License
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along with the GNU MP Library; see the file COPYING.LIB. If not, write to
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the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
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02110-1301, USA.
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IA-64 MPN SUBROUTINES
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This directory contains mpn functions for the IA-64 architecture.
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CODE ORGANIZATION
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mpn/ia64 itanium-2, and generic ia64
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The code here has been optimized primarily for Itanium 2. Very few Itanium 1
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chips were ever sold, and Itanium 2 is more powerful, so the latter is what
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we concentrate on.
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CHIP NOTES
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The IA-64 ISA keeps instructions three and three in 128 bit bundles.
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Programmers/compilers need to put explicit breaks `;;' when there are WAW or
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RAW dependencies, with some notable exceptions. Such "breaks" are typically
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at the end of a bundle, but can be put between operations within some bundle
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types too.
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The Itanium 1 and Itanium 2 implementations can under ideal conditions
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execute two bundles per cycle. The Itanium 2 allows 4 of these instructions
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to do integer operations, while the Itanium 2 allows all 6 to be integer
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operations.
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Taken cloop branches seem to insert a bubble into the pipeline most of the
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time on Itanium 1.
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Loads to the fp registers bypass the L1 cache and thus get extremely long
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latencies, 9 cycles on the Itanium 1 and 6 cycles on the Itanium 2.
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The software pipeline stuff using br.ctop instruction causes delays, since
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many issue slots are taken up by instructions with zero predicates, and
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since many extra instructions are needed to set things up. These features
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are clearly designed for code density, not speed.
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Misc pipeline limitations (Itanium 1):
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* The getf.sig instruction can only execute in M0.
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* At most four integer instructions/cycle.
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* Nops take up resources like any plain instructions.
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Misc pipeline limitations (Itanium 2):
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* The getf.sig instruction can only execute in M0.
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* Nops take up resources like any plain instructions.
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ASSEMBLY SYNTAX
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.align pads with nops in a text segment, but gas 2.14 and earlier
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incorrectly byte-swaps its nop bundle in big endian mode (eg. hpux), making
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it come out as break instructions. We use the ALIGN() macro in
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mpn/ia64/ia64-defs.m4 when it might be executed across. That macro
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suppresses any .align if the problem is detected by configure. Lack of
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alignment might hurt performance but will at least be correct.
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foo:: to create a global symbol is not accepted by gas. Use separate
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".global foo" and "foo:" instead.
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.global is the standard global directive. gas accepts .globl, but hpux "as"
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doesn't.
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.proc / .endp generates the appropriate .type and .size information for ELF,
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so the latter directives don't need to be given explicitly.
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.pred.rel "mutex"... is standard for annotating predicate register
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relationships. gas also accepts .pred.rel.mutex, but hpux "as" doesn't.
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.pred directives can't be put on a line with a label, like
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".Lfoo: .pred ...", the HP assembler on HP-UX 11.23 rejects that.
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gas is happy with it, and past versions of HP had seemed ok.
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// is the standard comment sequence, but we prefer "C" since it inhibits m4
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macro expansion. See comments in ia64-defs.m4.
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REGISTER USAGE
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Special:
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r0: constant 0
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r1: global pointer (gp)
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r8: return value
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r12: stack pointer (sp)
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r13: thread pointer (tp)
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Caller-saves: r8-r11 r14-r31 f6-f15 f32-f127
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Caller-saves but rotating: r32-
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REFERENCES
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Intel Itanium Architecture Software Developer's Manual, volumes 1 to 3,
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Intel document 245317-004, 245318-004, 245319-004 October 2002. Volume 1
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includes an Itanium optimization guide.
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Intel Itanium Processor-specific Application Binary Interface (ABI), Intel
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document 245370-003, May 2001. Describes C type sizes, dynamic linking,
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etc.
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Intel Itanium Architecture Assembly Language Reference Guide, Intel document
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248801-004, 2000-2002. Describes assembly instruction syntax and other
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directives.
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Itanium Software Conventions and Runtime Architecture Guide, Intel document
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245358-003, May 2001. Describes calling conventions, including stack
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unwinding requirements.
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Intel Itanium Processor Reference Manual for Software Optimization, Intel
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document 245473-003, November 2001.
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Intel Itanium-2 Processor Reference Manual for Software Development and
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Optimization, Intel document 251110-003, May 2004.
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All the above documents can be found online at
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http://developer.intel.com/design/itanium/manuals.htm
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----------------
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Local variables:
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mode: text
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fill-column: 76
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End:
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