303 lines
7.8 KiB
NASM
303 lines
7.8 KiB
NASM
dnl PowerPC-32/VMX and PowerPC-64/VMX mpn_and_n, mpn_andn_n, mpn_nand_n,
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dnl mpn_ior_n, mpn_iorn_n, mpn_nior_n, mpn_xor_n, mpn_xnor_n -- mpn bitwise
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dnl logical operations.
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dnl Copyright 2006 Free Software Foundation, Inc.
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dnl This file is part of the GNU MP Library.
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dnl The GNU MP Library is free software; you can redistribute it and/or modify
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dnl it under the terms of the GNU Lesser General Public License as published
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dnl by the Free Software Foundation; either version 2.1 of the License, or (at
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dnl your option) any later version.
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dnl The GNU MP Library is distributed in the hope that it will be useful, but
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dnl WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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dnl or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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dnl License for more details.
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dnl You should have received a copy of the GNU Lesser General Public License
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dnl along with the GNU MP Library; see the file COPYING.LIB. If not, write
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dnl to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
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dnl Boston, MA 02110-1301, USA.
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include(`../config.m4')
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C and,ior,andn,nior,xor iorn,xnor nand
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C cycles/limb cycles/limb cycles/limb
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C 7400,7410 (G4): 1.39 ? ?
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C 744x,745x (G4+): 1.14 1.39 1.39
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C 970: 1.7 2.0 2.0
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C STATUS
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C * Works for all sizes and alignment for 32-bit limbs.
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C * Works for n >= 4 for 64-bit limbs; untested for smaller operands.
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C * Current performance makes this pointless for 970
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C TODO
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C * Might want to make variants when just one of the source operands needs
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C vperm, and when neither needs it. The latter runs 50% faster on 7400.
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C * Idea: If the source operands are equally aligned, we could do the logops
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C first, then vperm before storing! That means we never need more than one
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C vperm, ever!
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C * Perhaps align `rp' after initial alignment loop?
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C * Instead of having scalar code in the beginning and end, consider using
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C read-modify-write vector code.
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C * Software pipeline? Hopefully not too important, this is hairy enough
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C already.
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C * At least be more clever about operand loading, i.e., load v operands before
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C u operands, since v operands are sometimes negated.
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define(`GMP_LIMB_BYTES', eval(GMP_LIMB_BITS/8))
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define(`LIMBS_PER_VR', eval(16/GMP_LIMB_BYTES))
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define(`LIMBS_PER_2VR', eval(32/GMP_LIMB_BYTES))
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define(`vnegb', `') C default neg-before to null
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define(`vnega', `') C default neg-before to null
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define(`OPERATION_nand_n',1)
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ifdef(`OPERATION_and_n',
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` define(`func', `mpn_and_n')
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define(`logopS',`and $1,$2,$3')
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define(`logop', `vand $1,$2,$3')')
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ifdef(`OPERATION_andn_n',
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` define(`func', `mpn_andn_n')
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define(`logopS',`andc $1,$2,$3')
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define(`logop', `vandc $1,$2,$3')')
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ifdef(`OPERATION_nand_n',
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` define(`func', `mpn_nand_n')
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define(`logopS',`nand $1,$2,$3')
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define(`logop', `vand $1,$2,$3')
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define(`vnega', `vnor $1,$2,$2')')
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ifdef(`OPERATION_ior_n',
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` define(`func', `mpn_ior_n')
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define(`logopS',`or $1,$2,$3')
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define(`logop', `vor $1,$2,$3')')
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ifdef(`OPERATION_iorn_n',
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` define(`func', `mpn_iorn_n')
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define(`logopS',`orc $1,$2,$3')
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define(`vnegb', `vnor $1,$2,$2')
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define(`logop', `vor $1,$2,$3')')
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ifdef(`OPERATION_nior_n',
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` define(`func', `mpn_nior_n')
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define(`logopS',`nor $1,$2,$3')
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define(`logop', `vnor $1,$2,$3')')
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ifdef(`OPERATION_xor_n',
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` define(`func', `mpn_xor_n')
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define(`logopS',`xor $1,$2,$3')
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define(`logop', `vxor $1,$2,$3')')
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ifdef(`OPERATION_xnor_n',
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` define(`func',`mpn_xnor_n')
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define(`logopS',`eqv $1,$2,$3')
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define(`vnegb', `vnor $1,$2,$2')
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define(`logop', `vxor $1,$2,$3')')
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ifelse(GMP_LIMB_BITS,`32',`
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define(`LIMB32',` $1')
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define(`LIMB64',`')
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',`
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define(`LIMB32',`')
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define(`LIMB64',` $1')
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')
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C INPUT PARAMETERS
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define(`rp', `r3')
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define(`up', `r4')
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define(`vp', `r5')
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define(`n', `r6')
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define(`us', `v8')
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define(`vs', `v9')
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ASM_START()
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PROLOGUE(func)
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LIMB32(`cmpwi cr0, n, 8 ')
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LIMB64(`cmpdi cr0, n, 4 ')
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bge L(big)
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mtctr n
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LIMB32(`lwz r8, 0(up) ')
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LIMB32(`lwz r9, 0(vp) ')
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LIMB32(`logopS( r0, r8, r9) ')
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LIMB32(`stw r0, 0(rp) ')
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LIMB32(`bdz L(endS) ')
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L(topS):
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LIMB32(`lwzu r8, 4(up) ')
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LIMB64(`ld r8, 0(up) ')
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LIMB64(`addi up, up, GMP_LIMB_BYTES ')
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LIMB32(`lwzu r9, 4(vp) ')
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LIMB64(`ld r9, 0(vp) ')
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LIMB64(`addi vp, vp, GMP_LIMB_BYTES ')
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logopS( r0, r8, r9)
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LIMB32(`stwu r0, 4(rp) ')
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LIMB64(`std r0, 0(rp) ')
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LIMB64(`addi rp, rp, GMP_LIMB_BYTES ')
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bdnz L(topS)
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L(endS):
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blr
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L(big): mfspr r12, 256
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oris r0, r12, 0xfffc C Set VRSAVE bit 0-13 FIXME
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mtspr 256, r0
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C First loop until the destination is 16-byte aligned. This will execute 0 or 1
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C times for 64-bit machines, and 0 to 3 times for 32-bit machines.
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LIMB32(`rlwinm. r0, rp, 30,30,31') C (rp >> 2) mod 4
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LIMB64(`rlwinm. r0, rp, 29,31,31') C (rp >> 3) mod 2
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beq L(aligned)
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subfic r7, r0, LIMBS_PER_VR
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LIMB32(`li r10, 0 ')
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subf n, r7, n
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L(top0):
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LIMB32(`lwz r8, 0(up) ')
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LIMB64(`ld r8, 0(up) ')
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addi up, up, GMP_LIMB_BYTES
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LIMB32(`lwz r9, 0(vp) ')
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LIMB64(`ld r9, 0(vp) ')
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addi vp, vp, GMP_LIMB_BYTES
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LIMB32(`addic. r7, r7, -1 ')
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logopS( r0, r8, r9)
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LIMB32(`stwx r0, r10, rp ')
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LIMB64(`std r0, 0(rp) ')
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LIMB32(`addi r10, r10, GMP_LIMB_BYTES')
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LIMB32(`bne L(top0) ')
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addi rp, rp, 16 C update rp, but preserve its alignment
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L(aligned):
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LIMB64(`srdi r7, n, 1 ') C loop count corresponding to n
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LIMB32(`srwi r7, n, 2 ') C loop count corresponding to n
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mtctr r7 C copy n to count register
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li r10, 16
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lvsl us, 0, up
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lvsl vs, 0, vp
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lvx v2, 0, up
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lvx v3, 0, vp
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bdnz L(gt1)
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lvx v0, r10, up
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lvx v1, r10, vp
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vperm v4, v2, v0, us
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vperm v5, v3, v1, vs
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vnegb( v5, v5)
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logop( v6, v4, v5)
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vnega( v6, v6)
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stvx v6, 0, rp
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addi up, up, 16
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addi vp, vp, 16
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addi rp, rp, 4
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b L(tail)
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L(gt1): addi up, up, 16
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addi vp, vp, 16
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L(top): lvx v0, 0, up
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lvx v1, 0, vp
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vperm v4, v2, v0, us
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vperm v5, v3, v1, vs
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vnegb( v5, v5)
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logop( v6, v4, v5)
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vnega( v6, v6)
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stvx v6, 0, rp
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bdz L(end)
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lvx v2, r10, up
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lvx v3, r10, vp
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vperm v4, v0, v2, us
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vperm v5, v1, v3, vs
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vnegb( v5, v5)
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logop( v6, v4, v5)
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vnega( v6, v6)
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stvx v6, r10, rp
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addi up, up, 32
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addi vp, vp, 32
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addi rp, rp, 32
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bdnz L(top)
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andi. r0, up, 15
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vxor v0, v0, v0
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beq 1f
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lvx v0, 0, up
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1: andi. r0, vp, 15
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vxor v1, v1, v1
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beq 1f
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lvx v1, 0, vp
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1: vperm v4, v2, v0, us
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vperm v5, v3, v1, vs
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vnegb( v5, v5)
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logop( v6, v4, v5)
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vnega( v6, v6)
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stvx v6, 0, rp
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addi rp, rp, 4
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b L(tail)
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L(end): andi. r0, up, 15
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vxor v2, v2, v2
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beq 1f
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lvx v2, r10, up
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1: andi. r0, vp, 15
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vxor v3, v3, v3
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beq 1f
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lvx v3, r10, vp
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1: vperm v4, v0, v2, us
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vperm v5, v1, v3, vs
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vnegb( v5, v5)
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logop( v6, v4, v5)
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vnega( v6, v6)
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stvx v6, r10, rp
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addi up, up, 16
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addi vp, vp, 16
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addi rp, rp, 20
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L(tail):
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LIMB32(`rlwinm. r7, n, 0,30,31 ') C r7 = n mod 4
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LIMB64(`rlwinm. r7, n, 0,31,31 ') C r7 = n mod 2
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beq L(ret)
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addi rp, rp, 15
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LIMB32(`rlwinm rp, rp, 0,0,27 ')
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LIMB64(`rldicr rp, rp, 0,59 ')
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li r10, 0
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L(top2):
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LIMB32(`lwzx r8, r10, up ')
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LIMB64(`ldx r8, r10, up ')
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LIMB32(`lwzx r9, r10, vp ')
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LIMB64(`ldx r9, r10, vp ')
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LIMB32(`addic. r7, r7, -1 ')
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logopS( r0, r8, r9)
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LIMB32(`stwx r0, r10, rp ')
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LIMB64(`std r0, 0(rp) ')
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LIMB32(`addi r10, r10, GMP_LIMB_BYTES')
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LIMB32(`bne L(top2) ')
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L(ret): mtspr 256, r12
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blr
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EPILOGUE()
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C This works for 64-bit PowerPC, since a limb ptr can only be aligned
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C in 2 relevant ways, which means we can always find a pair of aligned
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C pointers of rp, up, and vp.
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C process words until rp is 16-byte aligned
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C if (((up | vp) & 15) == 0)
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C process with VMX without any vperm
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C else if ((up & 15) != 0 && (vp & 15) != 0)
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C process with VMX using vperm on store data
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C else if ((up & 15) != 0)
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C process with VMX using vperm on up data
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C else
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C process with VMX using vperm on vp data
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C
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C rlwinm, r0, up, 0,28,31
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C rlwinm r0, vp, 0,28,31
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C cmpwi cr7, r0, 0
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C cror cr6, cr0, cr7
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C crand cr0, cr0, cr7
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C
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