220 lines
6.1 KiB
NASM
220 lines
6.1 KiB
NASM
dnl AMD K6-2 mpn_and_n, mpn_andn_n, mpn_nand_n, mpn_ior_n, mpn_iorn_n,
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dnl mpn_nior_n, mpn_xor_n, mpn_xnor_n -- mpn bitwise logical operations.
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dnl Copyright 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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dnl
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dnl This file is part of the GNU MP Library.
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dnl
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dnl The GNU MP Library is free software; you can redistribute it and/or
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dnl modify it under the terms of the GNU Lesser General Public License as
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dnl published by the Free Software Foundation; either version 2.1 of the
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dnl License, or (at your option) any later version.
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dnl
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dnl The GNU MP Library is distributed in the hope that it will be useful,
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dnl but WITHOUT ANY WARRANTY; without even the implied warranty of
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dnl MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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dnl Lesser General Public License for more details.
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dnl
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dnl You should have received a copy of the GNU Lesser General Public
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dnl License along with the GNU MP Library; see the file COPYING.LIB. If
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dnl not, write to the Free Software Foundation, Inc., 51 Franklin Street,
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dnl Fifth Floor, Boston, MA 02110-1301, USA.
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include(`../config.m4')
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NAILS_SUPPORT(0-31)
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C alignment dst/src1/src2, A=0mod8, N=4mod8
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C A/A/A A/A/N A/N/A A/N/N N/A/A N/A/N N/N/A N/N/N
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C
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C K6-2 1.2 1.5 1.5 1.2 1.2 1.5 1.5 1.2 and,andn,ior,xor
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C K6-2 1.5 1.75 2.0 1.75 1.75 2.0 1.75 1.5 iorn,xnor
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C K6-2 1.75 2.0 2.0 2.0 2.0 2.0 2.0 1.75 nand,nior
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C
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C K6 1.5 1.68 1.75 1.2 1.75 1.75 1.68 1.5 and,andn,ior,xor
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C K6 2.0 2.0 2.25 2.25 2.25 2.25 2.0 2.0 iorn,xnor
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C K6 2.0 2.25 2.25 2.25 2.25 2.25 2.25 2.0 nand,nior
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dnl M4_p and M4_i are the MMX and integer instructions
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dnl M4_*_neg_dst means whether to negate the final result before writing
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dnl M4_*_neg_src2 means whether to negate the src2 values before using them
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define(OPERATION_iorn_n,1)
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define(M4_choose_op,
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m4_assert_numargs(7)
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`ifdef(`OPERATION_$1',`
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define(`M4_function', `mpn_$1')
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define(`M4_operation', `$1')
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define(`M4_p', `$2')
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define(`M4_p_neg_dst', `$3')
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define(`M4_p_neg_src2',`$4')
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define(`M4_i', `$5')
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define(`M4_i_neg_dst', `$6')
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define(`M4_i_neg_src2',`$7')
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')')
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dnl xnor is done in "iorn" style because it's a touch faster than "nior"
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dnl style (the two are equivalent for xor).
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dnl
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dnl pandn can't be used with nails.
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M4_choose_op( and_n, pand,0,0, andl,0,0)
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ifelse(GMP_NAIL_BITS,0,
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`M4_choose_op(andn_n, pandn,0,0, andl,0,1)',
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`M4_choose_op(andn_n, pand,0,1, andl,0,1)')
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M4_choose_op( nand_n, pand,1,0, andl,1,0)
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M4_choose_op( ior_n, por,0,0, orl,0,0)
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M4_choose_op( iorn_n, por,0,1, orl,0,1)
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M4_choose_op( nior_n, por,1,0, orl,1,0)
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M4_choose_op( xor_n, pxor,0,0, xorl,0,0)
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M4_choose_op( xnor_n, pxor,0,1, xorl,0,1)
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ifdef(`M4_function',,
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`m4_error(`Unrecognised or undefined OPERATION symbol
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')')
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MULFUNC_PROLOGUE(mpn_and_n mpn_andn_n mpn_nand_n mpn_ior_n mpn_iorn_n mpn_nior_n mpn_xor_n mpn_xnor_n)
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C void M4_function (mp_ptr dst, mp_srcptr src1, mp_srcptr src2,
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C mp_size_t size);
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C
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C Do src1,size M4_operation src2,size, storing the result in dst,size.
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C
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C Unaligned movq loads and stores are a bit slower than aligned ones. The
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C test at the start of the routine checks the alignment of src1 and if
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C necessary processes one limb separately at the low end to make it aligned.
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C
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C The raw speeds without this alignment switch are as follows.
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C
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C alignment dst/src1/src2, A=0mod8, N=4mod8
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C A/A/A A/A/N A/N/A A/N/N N/A/A N/A/N N/N/A N/N/N
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C
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C K6 1.5 2.0 1.5 2.0 and,andn,ior,xor
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C K6 1.75 2.2 2.0 2.28 iorn,xnor
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C K6 2.0 2.25 2.35 2.28 nand,nior
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C
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C
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C Future:
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C
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C K6 can do one 64-bit load per cycle so each of these routines should be
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C able to approach 1.0 c/l, if aligned. The basic and/andn/ior/xor might be
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C able to get 1.0 with just a 4 limb loop, being 3 instructions per 2 limbs.
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C The others are 4 instructions per 2 limbs, and so can only approach 1.0
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C because there's nowhere to hide some loop control.
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defframe(PARAM_SIZE,16)
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defframe(PARAM_SRC2,12)
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defframe(PARAM_SRC1,8)
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defframe(PARAM_DST, 4)
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deflit(`FRAME',0)
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TEXT
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ALIGN(32)
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PROLOGUE(M4_function)
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movl PARAM_SIZE, %ecx
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pushl %ebx FRAME_pushl()
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movl PARAM_SRC1, %eax
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movl PARAM_SRC2, %ebx
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cmpl $1, %ecx
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movl PARAM_DST, %edx
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ja L(two_or_more)
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movl (%ebx), %ecx
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popl %ebx
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ifelse(M4_i_neg_src2,1,`notl_or_xorl_GMP_NUMB_MASK( %ecx)')
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M4_i (%eax), %ecx
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ifelse(M4_i_neg_dst,1,` notl_or_xorl_GMP_NUMB_MASK( %ecx)')
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movl %ecx, (%edx)
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ret
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L(two_or_more):
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C eax src1
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C ebx src2
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C ecx size
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C edx dst
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C esi
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C edi
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C ebp
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pushl %esi FRAME_pushl()
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testl $4, %eax
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jz L(alignment_ok)
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movl (%ebx), %esi
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addl $4, %ebx
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ifelse(M4_i_neg_src2,1,`notl_or_xorl_GMP_NUMB_MASK( %esi)')
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M4_i (%eax), %esi
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addl $4, %eax
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ifelse(M4_i_neg_dst,1,` notl_or_xorl_GMP_NUMB_MASK( %esi)')
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movl %esi, (%edx)
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addl $4, %edx
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decl %ecx
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L(alignment_ok):
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movl %ecx, %esi
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shrl %ecx
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jnz L(still_two_or_more)
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movl (%ebx), %ecx
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popl %esi
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ifelse(M4_i_neg_src2,1,`notl_or_xorl_GMP_NUMB_MASK( %ecx)')
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M4_i (%eax), %ecx
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ifelse(M4_i_neg_dst,1,` notl_or_xorl_GMP_NUMB_MASK( %ecx)')
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popl %ebx
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movl %ecx, (%edx)
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ret
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L(still_two_or_more):
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ifelse(eval(M4_p_neg_src2 || M4_p_neg_dst),1,`
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pcmpeqd %mm7, %mm7 C all ones
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ifelse(GMP_NAIL_BITS,0,,`psrld $GMP_NAIL_BITS, %mm7') C clear nails
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')
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ALIGN(16)
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L(top):
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C eax src1
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C ebx src2
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C ecx counter
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C edx dst
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C esi
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C edi
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C ebp
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C
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C carry bit is low of size
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movq -8(%ebx,%ecx,8), %mm0
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ifelse(M4_p_neg_src2,1,`pxor %mm7, %mm0')
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M4_p -8(%eax,%ecx,8), %mm0
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ifelse(M4_p_neg_dst,1,` pxor %mm7, %mm0')
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movq %mm0, -8(%edx,%ecx,8)
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loop L(top)
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jnc L(no_extra)
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movl -4(%ebx,%esi,4), %ebx
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ifelse(M4_i_neg_src2,1,`notl_or_xorl_GMP_NUMB_MASK( %ebx)')
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M4_i -4(%eax,%esi,4), %ebx
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ifelse(M4_i_neg_dst,1,` notl_or_xorl_GMP_NUMB_MASK( %ebx)')
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movl %ebx, -4(%edx,%esi,4)
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L(no_extra):
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popl %esi
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popl %ebx
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emms_or_femms
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ret
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EPILOGUE()
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