split up longlong into arches
This commit is contained in:
jasonmoxham
parent
9796a8ed3e
commit
a18af002d1
76
mpn/alpha/longlong.h
Normal file
76
mpn/alpha/longlong.h
Normal file
@ -0,0 +1,76 @@
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/* Most alpha-based machines, except Cray systems. */
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#if defined (__GNUC__)
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#define umul_ppmm(ph, pl, m0, m1) \
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do { \
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UDItype __m0 = (m0), __m1 = (m1); \
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__asm__ ("umulh %r1,%2,%0" \
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: "=r" (ph) \
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: "%rJ" (m0), "rI" (m1)); \
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(pl) = __m0 * __m1; \
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} while (0)
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#define UMUL_TIME 18
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#else /* ! __GNUC__ */
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#include <machine/builtins.h>
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#define umul_ppmm(ph, pl, m0, m1) \
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do { \
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UDItype __m0 = (m0), __m1 = (m1); \
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(ph) = __UMULH (m0, m1); \
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(pl) = __m0 * __m1; \
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} while (0)
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#endif
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#ifndef LONGLONG_STANDALONE
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#define udiv_qrnnd(q, r, n1, n0, d) \
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do { UWtype __di; \
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__di = __MPN(invert_limb) (d); \
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udiv_qrnnd_preinv (q, r, n1, n0, d, __di); \
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} while (0)
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#define UDIV_PREINV_ALWAYS 1
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#define UDIV_NEEDS_NORMALIZATION 1
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#define UDIV_TIME 220
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#endif /* LONGLONG_STANDALONE */
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/* clz_tab is required in all configurations, since mpn/alpha/cntlz.asm
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always goes into libmpir.so, even when not actually used. */
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#define COUNT_LEADING_ZEROS_NEED_CLZ_TAB
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#if defined (__GNUC__) && HAVE_HOST_CPU_alpha_CIX
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#define count_leading_zeros(COUNT,X) \
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__asm__("ctlz %1,%0" : "=r"(COUNT) : "r"(X))
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#define count_trailing_zeros(COUNT,X) \
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__asm__("cttz %1,%0" : "=r"(COUNT) : "r"(X))
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#endif /* clz/ctz using cix */
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#if ! defined (count_leading_zeros) \
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&& defined (__GNUC__) && ! defined (LONGLONG_STANDALONE)
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/* ALPHA_CMPBGE_0 gives "cmpbge $31,src,dst", ie. test src bytes == 0.
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"$31" is written explicitly in the asm, since an "r" constraint won't
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select reg 31. There seems no need to worry about "r31" syntax for cray,
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since gcc itself (pre-release 3.4) emits just $31 in various places. */
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#define ALPHA_CMPBGE_0(dst, src) \
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do { asm ("cmpbge $31, %1, %0" : "=r" (dst) : "r" (src)); } while (0)
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/* Zero bytes are turned into bits with cmpbge, a __clz_tab lookup counts
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them, locating the highest non-zero byte. A second __clz_tab lookup
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counts the leading zero bits in that byte, giving the result. */
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#define count_leading_zeros(count, x) \
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do { \
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UWtype __clz__b, __clz__c, __clz__x = (x); \
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ALPHA_CMPBGE_0 (__clz__b, __clz__x); /* zero bytes */ \
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__clz__b = __clz_tab [(__clz__b >> 1) ^ 0x7F]; /* 8 to 1 byte */ \
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__clz__b = __clz__b * 8 - 7; /* 57 to 1 shift */ \
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__clz__x >>= __clz__b; \
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__clz__c = __clz_tab [__clz__x]; /* 8 to 1 bit */ \
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__clz__b = 65 - __clz__b; \
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(count) = __clz__b - __clz__c; \
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} while (0)
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#define COUNT_LEADING_ZEROS_NEED_CLZ_TAB
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#endif /* clz using cmpbge */
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#if ! defined (count_leading_zeros) && ! defined (LONGLONG_STANDALONE)
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#if HAVE_ATTRIBUTE_CONST
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long __MPN(count_leading_zeros) _PROTO ((UDItype)) __attribute__ ((const));
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#else
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long __MPN(count_leading_zeros) _PROTO ((UDItype));
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#endif
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#define count_leading_zeros(count, x) \
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((count) = __MPN(count_leading_zeros) (x))
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#endif /* clz using mpn */
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89
mpn/arm/longlong.h
Normal file
89
mpn/arm/longlong.h
Normal file
@ -0,0 +1,89 @@
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#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
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__asm__ ("adds\t%1, %4, %5\n\tadc\t%0, %2, %3" \
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: "=r" (sh), "=&r" (sl) \
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: "r" (ah), "rI" (bh), "%r" (al), "rI" (bl) __CLOBBER_CC)
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#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
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do { \
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if (__builtin_constant_p (al)) \
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{ \
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if (__builtin_constant_p (ah)) \
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__asm__ ("rsbs\t%1, %5, %4\n\trsc\t%0, %3, %2" \
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: "=r" (sh), "=&r" (sl) \
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: "rI" (ah), "r" (bh), "rI" (al), "r" (bl) __CLOBBER_CC); \
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else \
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__asm__ ("rsbs\t%1, %5, %4\n\tsbc\t%0, %2, %3" \
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: "=r" (sh), "=&r" (sl) \
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: "r" (ah), "rI" (bh), "rI" (al), "r" (bl) __CLOBBER_CC); \
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} \
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else if (__builtin_constant_p (ah)) \
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{ \
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if (__builtin_constant_p (bl)) \
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__asm__ ("subs\t%1, %4, %5\n\trsc\t%0, %3, %2" \
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: "=r" (sh), "=&r" (sl) \
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: "rI" (ah), "r" (bh), "r" (al), "rI" (bl) __CLOBBER_CC); \
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else \
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__asm__ ("rsbs\t%1, %5, %4\n\trsc\t%0, %3, %2" \
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: "=r" (sh), "=&r" (sl) \
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: "rI" (ah), "r" (bh), "rI" (al), "r" (bl) __CLOBBER_CC); \
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} \
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else if (__builtin_constant_p (bl)) \
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{ \
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if (__builtin_constant_p (bh)) \
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__asm__ ("subs\t%1, %4, %5\n\tsbc\t%0, %2, %3" \
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: "=r" (sh), "=&r" (sl) \
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: "r" (ah), "rI" (bh), "r" (al), "rI" (bl) __CLOBBER_CC); \
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else \
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__asm__ ("subs\t%1, %4, %5\n\trsc\t%0, %3, %2" \
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: "=r" (sh), "=&r" (sl) \
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: "rI" (ah), "r" (bh), "r" (al), "rI" (bl) __CLOBBER_CC); \
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} \
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else /* only bh might be a constant */ \
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__asm__ ("subs\t%1, %4, %5\n\tsbc\t%0, %2, %3" \
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: "=r" (sh), "=&r" (sl) \
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: "r" (ah), "rI" (bh), "r" (al), "rI" (bl) __CLOBBER_CC);\
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} while (0)
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#if 1 || defined (__arm_m__) /* `M' series has widening multiply support */
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#define umul_ppmm(xh, xl, a, b) \
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__asm__ ("umull %0,%1,%2,%3" : "=&r" (xl), "=&r" (xh) : "r" (a), "r" (b))
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#define UMUL_TIME 5
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#define smul_ppmm(xh, xl, a, b) \
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__asm__ ("smull %0,%1,%2,%3" : "=&r" (xl), "=&r" (xh) : "r" (a), "r" (b))
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#ifndef LONGLONG_STANDALONE
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#define udiv_qrnnd(q, r, n1, n0, d) \
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do { UWtype __di; \
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__di = __MPN(invert_limb) (d); \
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udiv_qrnnd_preinv (q, r, n1, n0, d, __di); \
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} while (0)
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#define UDIV_PREINV_ALWAYS 1
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#define UDIV_NEEDS_NORMALIZATION 1
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#define UDIV_TIME 70
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#endif /* LONGLONG_STANDALONE */
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#else
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#define umul_ppmm(xh, xl, a, b) \
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__asm__ ("%@ Inlined umul_ppmm\n" \
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" mov %|r0, %2, lsr #16\n" \
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" mov %|r2, %3, lsr #16\n" \
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" bic %|r1, %2, %|r0, lsl #16\n" \
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" bic %|r2, %3, %|r2, lsl #16\n" \
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" mul %1, %|r1, %|r2\n" \
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" mul %|r2, %|r0, %|r2\n" \
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" mul %|r1, %0, %|r1\n" \
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" mul %0, %|r0, %0\n" \
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" adds %|r1, %|r2, %|r1\n" \
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" addcs %0, %0, #65536\n" \
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" adds %1, %1, %|r1, lsl #16\n" \
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" adc %0, %0, %|r1, lsr #16" \
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: "=&r" (xh), "=r" (xl) \
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: "r" (a), "r" (b) \
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: "r0", "r1", "r2")
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#define UMUL_TIME 20
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#ifndef LONGLONG_STANDALONE
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#define udiv_qrnnd(q, r, n1, n0, d) \
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do { UWtype __r; \
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(q) = __MPN(udiv_qrnnd) (&__r, (n1), (n0), (d)); \
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(r) = __r; \
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} while (0)
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extern UWtype __MPN(udiv_qrnnd) _PROTO ((UWtype *, UWtype, UWtype, UWtype));
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#define UDIV_TIME 200
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#endif /* LONGLONG_STANDALONE */
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#endif
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66
mpn/ia64/longlong.h
Normal file
66
mpn/ia64/longlong.h
Normal file
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/* This form encourages gcc (pre-release 3.4 at least) to emit predicated
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"sub r=r,r" and "sub r=r,r,1", giving a 2 cycle latency. The generic
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code using "al<bl" arithmetically comes out making an actual 0 or 1 in a
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register, which takes an extra cycle. */
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#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
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do { \
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UWtype __x; \
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__x = (al) - (bl); \
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if ((al) < (bl)) \
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(sh) = (ah) - (bh) - 1; \
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else \
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(sh) = (ah) - (bh); \
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(sl) = __x; \
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} while (0)
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#if defined (__GNUC__) && ! defined (__INTEL_COMPILER)
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/* Do both product parts in assembly, since that gives better code with
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all gcc versions. Some callers will just use the upper part, and in
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that situation we waste an instruction, but not any cycles. */
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#define umul_ppmm(ph, pl, m0, m1) \
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__asm__ ("xma.hu %0 = %2, %3, f0\n\txma.l %1 = %2, %3, f0" \
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: "=&f" (ph), "=f" (pl) \
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: "f" (m0), "f" (m1))
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#define UMUL_TIME 14
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#define count_leading_zeros(count, x) \
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do { \
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UWtype _x = (x), _y, _a, _c; \
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__asm__ ("mux1 %0 = %1, @rev" : "=r" (_y) : "r" (_x)); \
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__asm__ ("czx1.l %0 = %1" : "=r" (_a) : "r" (-_y | _y)); \
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_c = (_a - 1) << 3; \
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_x >>= _c; \
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if (_x >= 1 << 4) \
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_x >>= 4, _c += 4; \
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if (_x >= 1 << 2) \
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_x >>= 2, _c += 2; \
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_c += _x >> 1; \
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(count) = W_TYPE_SIZE - 1 - _c; \
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} while (0)
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/* similar to what gcc does for __builtin_ffs, but 0 based rather than 1
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based, and we don't need a special case for x==0 here */
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#define count_trailing_zeros(count, x) \
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do { \
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UWtype __ctz_x = (x); \
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__asm__ ("popcnt %0 = %1" \
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: "=r" (count) \
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: "r" ((__ctz_x-1) & ~__ctz_x)); \
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} while (0)
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#endif
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#if defined (__INTEL_COMPILER)
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#include <ia64intrin.h>
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#define umul_ppmm(ph, pl, m0, m1) \
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do { \
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UWtype _m0 = (m0), _m1 = (m1); \
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ph = _m64_xmahu (_m0, _m1, 0); \
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pl = _m0 * _m1; \
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} while (0)
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#endif
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#ifndef LONGLONG_STANDALONE
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#define udiv_qrnnd(q, r, n1, n0, d) \
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do { UWtype __di; \
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__di = __MPN(invert_limb) (d); \
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udiv_qrnnd_preinv (q, r, n1, n0, d, __di); \
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} while (0)
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#define UDIV_PREINV_ALWAYS 1
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#define UDIV_NEEDS_NORMALIZATION 1
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#endif
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#define UDIV_TIME 220
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77
mpn/m68k/longlong.h
Normal file
77
mpn/m68k/longlong.h
Normal file
@ -0,0 +1,77 @@
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#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
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__asm__ ("add%.l %5,%1\n\taddx%.l %3,%0" \
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: "=d" (sh), "=&d" (sl) \
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: "0" ((USItype)(ah)), "d" ((USItype)(bh)), \
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"%1" ((USItype)(al)), "g" ((USItype)(bl)))
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#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
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__asm__ ("sub%.l %5,%1\n\tsubx%.l %3,%0" \
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: "=d" (sh), "=&d" (sl) \
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: "0" ((USItype)(ah)), "d" ((USItype)(bh)), \
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"1" ((USItype)(al)), "g" ((USItype)(bl)))
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/* The '020, '030, '040 and CPU32 have 32x32->64 and 64/32->32q-32r. */
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#if defined (__mc68020__) || defined(mc68020) \
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|| defined (__mc68030__) || defined (mc68030) \
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|| defined (__mc68040__) || defined (mc68040) \
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|| defined (__mcpu32__) || defined (mcpu32) \
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|| defined (__NeXT__)
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#define umul_ppmm(w1, w0, u, v) \
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__asm__ ("mulu%.l %3,%1:%0" \
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: "=d" (w0), "=d" (w1) \
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: "%0" ((USItype)(u)), "dmi" ((USItype)(v)))
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#define UMUL_TIME 45
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#define udiv_qrnnd(q, r, n1, n0, d) \
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__asm__ ("divu%.l %4,%1:%0" \
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: "=d" (q), "=d" (r) \
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: "0" ((USItype)(n0)), "1" ((USItype)(n1)), "dmi" ((USItype)(d)))
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#define UDIV_TIME 90
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#define sdiv_qrnnd(q, r, n1, n0, d) \
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__asm__ ("divs%.l %4,%1:%0" \
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: "=d" (q), "=d" (r) \
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: "0" ((USItype)(n0)), "1" ((USItype)(n1)), "dmi" ((USItype)(d)))
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#else /* for other 68k family members use 16x16->32 multiplication */
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#define umul_ppmm(xh, xl, a, b) \
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do { USItype __umul_tmp1, __umul_tmp2; \
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__asm__ ("| Inlined umul_ppmm\n" \
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" move%.l %5,%3\n" \
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" move%.l %2,%0\n" \
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" move%.w %3,%1\n" \
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" swap %3\n" \
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" swap %0\n" \
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" mulu%.w %2,%1\n" \
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" mulu%.w %3,%0\n" \
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" mulu%.w %2,%3\n" \
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" swap %2\n" \
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" mulu%.w %5,%2\n" \
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" add%.l %3,%2\n" \
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" jcc 1f\n" \
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" add%.l %#0x10000,%0\n" \
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"1: move%.l %2,%3\n" \
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" clr%.w %2\n" \
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" swap %2\n" \
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" swap %3\n" \
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" clr%.w %3\n" \
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" add%.l %3,%1\n" \
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" addx%.l %2,%0\n" \
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" | End inlined umul_ppmm" \
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: "=&d" (xh), "=&d" (xl), \
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"=d" (__umul_tmp1), "=&d" (__umul_tmp2) \
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: "%2" ((USItype)(a)), "d" ((USItype)(b))); \
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} while (0)
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#define UMUL_TIME 100
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#define UDIV_TIME 400
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#endif /* not mc68020 */
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/* The '020, '030, '040 and '060 have bitfield insns.
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GCC 3.4 defines __mc68020__ when in CPU32 mode, check for __mcpu32__ to
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exclude bfffo on that chip (bitfield insns not available). */
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#if (defined (__mc68020__) || defined (mc68020) \
|
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|| defined (__mc68030__) || defined (mc68030) \
|
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|| defined (__mc68040__) || defined (mc68040) \
|
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|| defined (__mc68060__) || defined (mc68060) \
|
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|| defined (__NeXT__)) \
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&& ! defined (__mcpu32__)
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#define count_leading_zeros(count, x) \
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__asm__ ("bfffo %1{%b2:%b2},%0" \
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: "=d" (count) \
|
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: "od" ((USItype) (x)), "n" (0))
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#define COUNT_LEADING_ZEROS_0 32
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#endif
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39
mpn/mips32/longlong.h
Normal file
39
mpn/mips32/longlong.h
Normal file
@ -0,0 +1,39 @@
|
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/* longlong.h -- definitions for mixed size 32/64 bit arithmetic.
|
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|
||||
Copyright 1991, 1992, 1993, 1994, 1996, 1997, 1999, 2000, 2001, 2002, 2003,
|
||||
2004, 2005 , 2007 , 2008 , 2009 Free Software Foundation, Inc.
|
||||
|
||||
This file is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU Lesser General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or (at your
|
||||
option) any later version.
|
||||
|
||||
This file is distributed in the hope that it will be useful, but
|
||||
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
||||
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
|
||||
License for more details.
|
||||
|
||||
You should have received a copy of the GNU Lesser General Public License
|
||||
along with this file; see the file COPYING.LIB. If not, write to
|
||||
the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
||||
MA 02110-1301, USA. */
|
||||
|
||||
#if __GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 4)
|
||||
#define umul_ppmm(w1, w0, u, v) \
|
||||
do { \
|
||||
UDItype __ll = (UDItype)(u) * (v); \
|
||||
w1 = __ll >> 32; \
|
||||
w0 = __ll; \
|
||||
} while (0)
|
||||
#endif
|
||||
#if !defined (umul_ppmm) && (__GNUC__ > 2 || __GNUC_MINOR__ >= 7)
|
||||
#define umul_ppmm(w1, w0, u, v) \
|
||||
__asm__ ("multu %2,%3" : "=l" (w0), "=h" (w1) : "d" (u), "d" (v))
|
||||
#endif
|
||||
#if !defined (umul_ppmm)
|
||||
#define umul_ppmm(w1, w0, u, v) \
|
||||
__asm__ ("multu %2,%3\n\tmflo %0\n\tmfhi %1" \
|
||||
: "=d" (w0), "=d" (w1) : "d" (u), "d" (v))
|
||||
#endif
|
||||
#define UMUL_TIME 10
|
||||
#define UDIV_TIME 100
|
||||
40
mpn/mips64/longlong.h
Normal file
40
mpn/mips64/longlong.h
Normal file
@ -0,0 +1,40 @@
|
||||
/* longlong.h -- definitions for mixed size 32/64 bit arithmetic.
|
||||
|
||||
Copyright 1991, 1992, 1993, 1994, 1996, 1997, 1999, 2000, 2001, 2002, 2003,
|
||||
2004, 2005 , 2007 , 2008 , 2009 Free Software Foundation, Inc.
|
||||
|
||||
This file is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU Lesser General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or (at your
|
||||
option) any later version.
|
||||
|
||||
This file is distributed in the hope that it will be useful, but
|
||||
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
||||
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
|
||||
License for more details.
|
||||
|
||||
You should have received a copy of the GNU Lesser General Public License
|
||||
along with this file; see the file COPYING.LIB. If not, write to
|
||||
the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
||||
MA 02110-1301, USA. */
|
||||
|
||||
#if __GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 4)
|
||||
#define umul_ppmm(w1, w0, u, v) \
|
||||
do { \
|
||||
typedef unsigned int __ll_UTItype __attribute__((mode(TI))); \
|
||||
__ll_UTItype __ll = (__ll_UTItype)(u) * (v); \
|
||||
w1 = __ll >> 64; \
|
||||
w0 = __ll; \
|
||||
} while (0)
|
||||
#endif
|
||||
#if !defined (umul_ppmm) && (__GNUC__ > 2 || __GNUC_MINOR__ >= 7)
|
||||
#define umul_ppmm(w1, w0, u, v) \
|
||||
__asm__ ("dmultu %2,%3" : "=l" (w0), "=h" (w1) : "d" (u), "d" (v))
|
||||
#endif
|
||||
#if !defined (umul_ppmm)
|
||||
#define umul_ppmm(w1, w0, u, v) \
|
||||
__asm__ ("dmultu %2,%3\n\tmflo %0\n\tmfhi %1" \
|
||||
: "=d" (w0), "=d" (w1) : "d" (u), "d" (v))
|
||||
#endif
|
||||
#define UMUL_TIME 20
|
||||
#define UDIV_TIME 140
|
||||
45
mpn/pa32/longlong.h
Normal file
45
mpn/pa32/longlong.h
Normal file
@ -0,0 +1,45 @@
|
||||
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
|
||||
__asm__ ("add%I5 %5,%r4,%1\n\taddc %r2,%r3,%0" \
|
||||
: "=r" (sh), "=&r" (sl) \
|
||||
: "rM" (ah), "rM" (bh), "%rM" (al), "rI" (bl))
|
||||
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
|
||||
__asm__ ("sub%I4 %4,%r5,%1\n\tsubb %r2,%r3,%0" \
|
||||
: "=r" (sh), "=&r" (sl) \
|
||||
: "rM" (ah), "rM" (bh), "rI" (al), "rM" (bl))
|
||||
#if defined (_PA_RISC1_1)
|
||||
#define umul_ppmm(wh, wl, u, v) \
|
||||
do { \
|
||||
union {UDItype __ll; \
|
||||
struct {USItype __h, __l;} __i; \
|
||||
} __x; \
|
||||
__asm__ ("xmpyu %1,%2,%0" : "=*f" (__x.__ll) : "*f" (u), "*f" (v)); \
|
||||
(wh) = __x.__i.__h; \
|
||||
(wl) = __x.__i.__l; \
|
||||
} while (0)
|
||||
#define UMUL_TIME 8
|
||||
#define UDIV_TIME 60
|
||||
#else
|
||||
#define UMUL_TIME 40
|
||||
#define UDIV_TIME 80
|
||||
#endif
|
||||
#define count_leading_zeros(count, x) \
|
||||
do { \
|
||||
USItype __tmp; \
|
||||
__asm__ ( \
|
||||
"ldi 1,%0\n" \
|
||||
" extru,= %1,15,16,%%r0 ; Bits 31..16 zero?\n" \
|
||||
" extru,tr %1,15,16,%1 ; No. Shift down, skip add.\n" \
|
||||
" ldo 16(%0),%0 ; Yes. Perform add.\n" \
|
||||
" extru,= %1,23,8,%%r0 ; Bits 15..8 zero?\n" \
|
||||
" extru,tr %1,23,8,%1 ; No. Shift down, skip add.\n" \
|
||||
" ldo 8(%0),%0 ; Yes. Perform add.\n" \
|
||||
" extru,= %1,27,4,%%r0 ; Bits 7..4 zero?\n" \
|
||||
" extru,tr %1,27,4,%1 ; No. Shift down, skip add.\n" \
|
||||
" ldo 4(%0),%0 ; Yes. Perform add.\n" \
|
||||
" extru,= %1,29,2,%%r0 ; Bits 3..2 zero?\n" \
|
||||
" extru,tr %1,29,2,%1 ; No. Shift down, skip add.\n" \
|
||||
" ldo 2(%0),%0 ; Yes. Perform add.\n" \
|
||||
" extru %1,30,1,%1 ; Extract bit 1.\n" \
|
||||
" sub %0,%1,%0 ; Subtract it.\n" \
|
||||
: "=r" (count), "=r" (__tmp) : "1" (x)); \
|
||||
} while (0)
|
||||
8
mpn/pa64/longlong.h
Normal file
8
mpn/pa64/longlong.h
Normal file
@ -0,0 +1,8 @@
|
||||
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
|
||||
__asm__ ("add%I5 %5,%r4,%1\n\tadd,dc %r2,%r3,%0" \
|
||||
: "=r" (sh), "=&r" (sl) \
|
||||
: "rM" (ah), "rM" (bh), "%rM" (al), "rI" (bl))
|
||||
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
|
||||
__asm__ ("sub%I4 %4,%r5,%1\n\tsub,db %r2,%r3,%0" \
|
||||
: "=r" (sh), "=&r" (sl) \
|
||||
: "rM" (ah), "rM" (bh), "rI" (al), "rM" (bl))
|
||||
60
mpn/powerpc32/longlong.h
Normal file
60
mpn/powerpc32/longlong.h
Normal file
@ -0,0 +1,60 @@
|
||||
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
|
||||
do { \
|
||||
if (__builtin_constant_p (bh) && (bh) == 0) \
|
||||
__asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{aze|addze} %0,%2" \
|
||||
: "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
|
||||
else if (__builtin_constant_p (bh) && (bh) == ~(USItype) 0) \
|
||||
__asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{ame|addme} %0,%2" \
|
||||
: "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
|
||||
else \
|
||||
__asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3" \
|
||||
: "=r" (sh), "=&r" (sl) \
|
||||
: "r" (ah), "r" (bh), "%r" (al), "rI" (bl)); \
|
||||
} while (0)
|
||||
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
|
||||
do { \
|
||||
if (__builtin_constant_p (ah) && (ah) == 0) \
|
||||
__asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfze|subfze} %0,%2" \
|
||||
: "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
|
||||
else if (__builtin_constant_p (ah) && (ah) == ~(USItype) 0) \
|
||||
__asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfme|subfme} %0,%2" \
|
||||
: "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
|
||||
else if (__builtin_constant_p (bh) && (bh) == 0) \
|
||||
__asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{ame|addme} %0,%2" \
|
||||
: "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
|
||||
else if (__builtin_constant_p (bh) && (bh) == ~(USItype) 0) \
|
||||
__asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{aze|addze} %0,%2" \
|
||||
: "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
|
||||
else \
|
||||
__asm__ ("{sf%I4|subf%I4c} %1,%5,%4\n\t{sfe|subfe} %0,%3,%2" \
|
||||
: "=r" (sh), "=&r" (sl) \
|
||||
: "r" (ah), "r" (bh), "rI" (al), "r" (bl)); \
|
||||
} while (0)
|
||||
#define count_leading_zeros(count, x) \
|
||||
__asm__ ("{cntlz|cntlzw} %0,%1" : "=r" (count) : "r" (x))
|
||||
#define COUNT_LEADING_ZEROS_0 32
|
||||
#if HAVE_HOST_CPU_FAMILY_powerpc
|
||||
#define umul_ppmm(ph, pl, m0, m1) \
|
||||
do { \
|
||||
USItype __m0 = (m0), __m1 = (m1); \
|
||||
__asm__ ("mulhwu %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
|
||||
(pl) = __m0 * __m1; \
|
||||
} while (0)
|
||||
#define UMUL_TIME 15
|
||||
#define smul_ppmm(ph, pl, m0, m1) \
|
||||
do { \
|
||||
SItype __m0 = (m0), __m1 = (m1); \
|
||||
__asm__ ("mulhw %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
|
||||
(pl) = __m0 * __m1; \
|
||||
} while (0)
|
||||
#define SMUL_TIME 14
|
||||
#define UDIV_TIME 120
|
||||
#else
|
||||
#define UMUL_TIME 8
|
||||
#define smul_ppmm(xh, xl, m0, m1) \
|
||||
__asm__ ("mul %0,%2,%3" : "=r" (xh), "=q" (xl) : "r" (m0), "r" (m1))
|
||||
#define SMUL_TIME 4
|
||||
#define sdiv_qrnnd(q, r, nh, nl, d) \
|
||||
__asm__ ("div %0,%2,%4" : "=r" (q), "=q" (r) : "r" (nh), "1" (nl), "r" (d))
|
||||
#define UDIV_TIME 100
|
||||
#endif
|
||||
54
mpn/powerpc64/longlong.h
Normal file
54
mpn/powerpc64/longlong.h
Normal file
@ -0,0 +1,54 @@
|
||||
#if !defined (_LONG_LONG_LIMB)
|
||||
/* _LONG_LONG_LIMB is ABI=mode32 where adde operates on 32-bit values. So
|
||||
use adde etc only when not _LONG_LONG_LIMB. */
|
||||
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
|
||||
do { \
|
||||
if (__builtin_constant_p (bh) && (bh) == 0) \
|
||||
__asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{aze|addze} %0,%2" \
|
||||
: "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
|
||||
else if (__builtin_constant_p (bh) && (bh) == ~(UDItype) 0) \
|
||||
__asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{ame|addme} %0,%2" \
|
||||
: "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
|
||||
else \
|
||||
__asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3" \
|
||||
: "=r" (sh), "=&r" (sl) \
|
||||
: "r" (ah), "r" (bh), "%r" (al), "rI" (bl)); \
|
||||
} while (0)
|
||||
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
|
||||
do { \
|
||||
if (__builtin_constant_p (ah) && (ah) == 0) \
|
||||
__asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfze|subfze} %0,%2" \
|
||||
: "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
|
||||
else if (__builtin_constant_p (ah) && (ah) == ~(UDItype) 0) \
|
||||
__asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfme|subfme} %0,%2" \
|
||||
: "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
|
||||
else if (__builtin_constant_p (bh) && (bh) == 0) \
|
||||
__asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{ame|addme} %0,%2" \
|
||||
: "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
|
||||
else if (__builtin_constant_p (bh) && (bh) == ~(UDItype) 0) \
|
||||
__asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{aze|addze} %0,%2" \
|
||||
: "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
|
||||
else \
|
||||
__asm__ ("{sf%I4|subf%I4c} %1,%5,%4\n\t{sfe|subfe} %0,%3,%2" \
|
||||
: "=r" (sh), "=&r" (sl) \
|
||||
: "r" (ah), "r" (bh), "rI" (al), "r" (bl)); \
|
||||
} while (0)
|
||||
#endif /* ! _LONG_LONG_LIMB */
|
||||
#define count_leading_zeros(count, x) \
|
||||
__asm__ ("cntlzd %0,%1" : "=r" (count) : "r" (x))
|
||||
#define COUNT_LEADING_ZEROS_0 64
|
||||
#define umul_ppmm(ph, pl, m0, m1) \
|
||||
do { \
|
||||
UDItype __m0 = (m0), __m1 = (m1); \
|
||||
__asm__ ("mulhdu %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
|
||||
(pl) = __m0 * __m1; \
|
||||
} while (0)
|
||||
#define UMUL_TIME 15
|
||||
#define smul_ppmm(ph, pl, m0, m1) \
|
||||
do { \
|
||||
DItype __m0 = (m0), __m1 = (m1); \
|
||||
__asm__ ("mulhd %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
|
||||
(pl) = __m0 * __m1; \
|
||||
} while (0)
|
||||
#define SMUL_TIME 14 /* ??? */
|
||||
#define UDIV_TIME 120 /* ??? */
|
||||
21
mpn/s390/longlong.h
Normal file
21
mpn/s390/longlong.h
Normal file
@ -0,0 +1,21 @@
|
||||
#define smul_ppmm(xh, xl, m0, m1) \
|
||||
do { \
|
||||
union {DItype __ll; \
|
||||
struct {USItype __h, __l;} __i; \
|
||||
} __x; \
|
||||
__asm__ ("lr %N0,%1\n\tmr %0,%2" \
|
||||
: "=&r" (__x.__ll) \
|
||||
: "r" (m0), "r" (m1)); \
|
||||
(xh) = __x.__i.__h; (xl) = __x.__i.__l; \
|
||||
} while (0)
|
||||
#define sdiv_qrnnd(q, r, n1, n0, d) \
|
||||
do { \
|
||||
union {DItype __ll; \
|
||||
struct {USItype __h, __l;} __i; \
|
||||
} __x; \
|
||||
__x.__i.__h = n1; __x.__i.__l = n0; \
|
||||
__asm__ ("dr %0,%2" \
|
||||
: "=r" (__x.__ll) \
|
||||
: "0" (__x.__ll), "r" (d)); \
|
||||
(q) = __x.__i.__l; (r) = __x.__i.__h; \
|
||||
} while (0)
|
||||
4
mpn/sh/longlong.h
Normal file
4
mpn/sh/longlong.h
Normal file
@ -0,0 +1,4 @@
|
||||
#define umul_ppmm(w1, w0, u, v) \
|
||||
__asm__ ("dmulu.l %2,%3\n\tsts macl,%1\n\tsts mach,%0" \
|
||||
: "=r" (w1), "=r" (w0) : "r" (u), "r" (v) : "macl", "mach")
|
||||
#define UMUL_TIME 5
|
||||
180
mpn/sparc32/longlong.h
Normal file
180
mpn/sparc32/longlong.h
Normal file
@ -0,0 +1,180 @@
|
||||
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
|
||||
__asm__ ("addcc %r4,%5,%1\n\taddx %r2,%3,%0" \
|
||||
: "=r" (sh), "=&r" (sl) \
|
||||
: "rJ" (ah), "rI" (bh),"%rJ" (al), "rI" (bl) \
|
||||
__CLOBBER_CC)
|
||||
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
|
||||
__asm__ ("subcc %r4,%5,%1\n\tsubx %r2,%3,%0" \
|
||||
: "=r" (sh), "=&r" (sl) \
|
||||
: "rJ" (ah), "rI" (bh), "rJ" (al), "rI" (bl) \
|
||||
__CLOBBER_CC)
|
||||
/* FIXME: When gcc -mcpu=v9 is used on solaris, gcc/config/sol2-sld-64.h
|
||||
doesn't define anything to indicate that to us, it only sets __sparcv8. */
|
||||
#if defined (__sparc_v9__) || defined (__sparcv9)
|
||||
/* Perhaps we should use floating-point operations here? */
|
||||
#if 0
|
||||
/* Triggers a bug making mpz/tests/t-gcd.c fail.
|
||||
Perhaps we simply need explicitly zero-extend the inputs? */
|
||||
#define umul_ppmm(w1, w0, u, v) \
|
||||
__asm__ ("mulx %2,%3,%%g1; srl %%g1,0,%1; srlx %%g1,32,%0" : \
|
||||
"=r" (w1), "=r" (w0) : "r" (u), "r" (v) : "g1")
|
||||
#else
|
||||
/* Use v8 umul until above bug is fixed. */
|
||||
#define umul_ppmm(w1, w0, u, v) \
|
||||
__asm__ ("umul %2,%3,%1;rd %%y,%0" : "=r" (w1), "=r" (w0) : "r" (u), "r" (v))
|
||||
#endif
|
||||
/* Use a plain v8 divide for v9. */
|
||||
#define udiv_qrnnd(q, r, n1, n0, d) \
|
||||
do { \
|
||||
USItype __q; \
|
||||
__asm__ ("mov %1,%%y;nop;nop;nop;udiv %2,%3,%0" \
|
||||
: "=r" (__q) : "r" (n1), "r" (n0), "r" (d)); \
|
||||
(r) = (n0) - __q * (d); \
|
||||
(q) = __q; \
|
||||
} while (0)
|
||||
#else
|
||||
#if defined (__sparc_v8__) /* gcc normal */ \
|
||||
|| defined (__sparcv8) /* gcc solaris */ \
|
||||
|| HAVE_HOST_CPU_supersparc
|
||||
/* Don't match immediate range because, 1) it is not often useful,
|
||||
2) the 'I' flag thinks of the range as a 13 bit signed interval,
|
||||
while we want to match a 13 bit interval, sign extended to 32 bits,
|
||||
but INTERPRETED AS UNSIGNED. */
|
||||
#define umul_ppmm(w1, w0, u, v) \
|
||||
__asm__ ("umul %2,%3,%1;rd %%y,%0" : "=r" (w1), "=r" (w0) : "r" (u), "r" (v))
|
||||
#define UMUL_TIME 5
|
||||
|
||||
#if HAVE_HOST_CPU_supersparc
|
||||
#define UDIV_TIME 60 /* SuperSPARC timing */
|
||||
#else
|
||||
/* Don't use this on SuperSPARC because its udiv only handles 53 bit
|
||||
dividends and will trap to the kernel for the rest. */
|
||||
#define udiv_qrnnd(q, r, n1, n0, d) \
|
||||
do { \
|
||||
USItype __q; \
|
||||
__asm__ ("mov %1,%%y;nop;nop;nop;udiv %2,%3,%0" \
|
||||
: "=r" (__q) : "r" (n1), "r" (n0), "r" (d)); \
|
||||
(r) = (n0) - __q * (d); \
|
||||
(q) = __q; \
|
||||
} while (0)
|
||||
#define UDIV_TIME 25
|
||||
#endif /* HAVE_HOST_CPU_supersparc */
|
||||
|
||||
#else /* ! __sparc_v8__ */
|
||||
#if defined (__sparclite__)
|
||||
/* This has hardware multiply but not divide. It also has two additional
|
||||
instructions scan (ffs from high bit) and divscc. */
|
||||
#define umul_ppmm(w1, w0, u, v) \
|
||||
__asm__ ("umul %2,%3,%1;rd %%y,%0" : "=r" (w1), "=r" (w0) : "r" (u), "r" (v))
|
||||
#define UMUL_TIME 5
|
||||
#define udiv_qrnnd(q, r, n1, n0, d) \
|
||||
__asm__ ("! Inlined udiv_qrnnd\n" \
|
||||
" wr %%g0,%2,%%y ! Not a delayed write for sparclite\n" \
|
||||
" tst %%g0\n" \
|
||||
" divscc %3,%4,%%g1\n" \
|
||||
" divscc %%g1,%4,%%g1\n" \
|
||||
" divscc %%g1,%4,%%g1\n" \
|
||||
" divscc %%g1,%4,%%g1\n" \
|
||||
" divscc %%g1,%4,%%g1\n" \
|
||||
" divscc %%g1,%4,%%g1\n" \
|
||||
" divscc %%g1,%4,%%g1\n" \
|
||||
" divscc %%g1,%4,%%g1\n" \
|
||||
" divscc %%g1,%4,%%g1\n" \
|
||||
" divscc %%g1,%4,%%g1\n" \
|
||||
" divscc %%g1,%4,%%g1\n" \
|
||||
" divscc %%g1,%4,%%g1\n" \
|
||||
" divscc %%g1,%4,%%g1\n" \
|
||||
" divscc %%g1,%4,%%g1\n" \
|
||||
" divscc %%g1,%4,%%g1\n" \
|
||||
" divscc %%g1,%4,%%g1\n" \
|
||||
" divscc %%g1,%4,%%g1\n" \
|
||||
" divscc %%g1,%4,%%g1\n" \
|
||||
" divscc %%g1,%4,%%g1\n" \
|
||||
" divscc %%g1,%4,%%g1\n" \
|
||||
" divscc %%g1,%4,%%g1\n" \
|
||||
" divscc %%g1,%4,%%g1\n" \
|
||||
" divscc %%g1,%4,%%g1\n" \
|
||||
" divscc %%g1,%4,%%g1\n" \
|
||||
" divscc %%g1,%4,%%g1\n" \
|
||||
" divscc %%g1,%4,%%g1\n" \
|
||||
" divscc %%g1,%4,%%g1\n" \
|
||||
" divscc %%g1,%4,%%g1\n" \
|
||||
" divscc %%g1,%4,%%g1\n" \
|
||||
" divscc %%g1,%4,%%g1\n" \
|
||||
" divscc %%g1,%4,%%g1\n" \
|
||||
" divscc %%g1,%4,%0\n" \
|
||||
" rd %%y,%1\n" \
|
||||
" bl,a 1f\n" \
|
||||
" add %1,%4,%1\n" \
|
||||
"1: ! End of inline udiv_qrnnd" \
|
||||
: "=r" (q), "=r" (r) : "r" (n1), "r" (n0), "rI" (d) \
|
||||
: "%g1" __AND_CLOBBER_CC)
|
||||
#define UDIV_TIME 37
|
||||
#define count_leading_zeros(count, x) \
|
||||
__asm__ ("scan %1,1,%0" : "=r" (count) : "r" (x))
|
||||
/* Early sparclites return 63 for an argument of 0, but they warn that future
|
||||
implementations might change this. Therefore, leave COUNT_LEADING_ZEROS_0
|
||||
undefined. */
|
||||
#endif /* __sparclite__ */
|
||||
#endif /* __sparc_v8__ */
|
||||
#endif /* __sparc_v9__ */
|
||||
/* Default to sparc v7 versions of umul_ppmm and udiv_qrnnd. */
|
||||
#ifndef umul_ppmm
|
||||
#define umul_ppmm(w1, w0, u, v) \
|
||||
__asm__ ("! Inlined umul_ppmm\n" \
|
||||
" wr %%g0,%2,%%y ! SPARC has 0-3 delay insn after a wr\n" \
|
||||
" sra %3,31,%%g2 ! Don't move this insn\n" \
|
||||
" and %2,%%g2,%%g2 ! Don't move this insn\n" \
|
||||
" andcc %%g0,0,%%g1 ! Don't move this insn\n" \
|
||||
" mulscc %%g1,%3,%%g1\n" \
|
||||
" mulscc %%g1,%3,%%g1\n" \
|
||||
" mulscc %%g1,%3,%%g1\n" \
|
||||
" mulscc %%g1,%3,%%g1\n" \
|
||||
" mulscc %%g1,%3,%%g1\n" \
|
||||
" mulscc %%g1,%3,%%g1\n" \
|
||||
" mulscc %%g1,%3,%%g1\n" \
|
||||
" mulscc %%g1,%3,%%g1\n" \
|
||||
" mulscc %%g1,%3,%%g1\n" \
|
||||
" mulscc %%g1,%3,%%g1\n" \
|
||||
" mulscc %%g1,%3,%%g1\n" \
|
||||
" mulscc %%g1,%3,%%g1\n" \
|
||||
" mulscc %%g1,%3,%%g1\n" \
|
||||
" mulscc %%g1,%3,%%g1\n" \
|
||||
" mulscc %%g1,%3,%%g1\n" \
|
||||
" mulscc %%g1,%3,%%g1\n" \
|
||||
" mulscc %%g1,%3,%%g1\n" \
|
||||
" mulscc %%g1,%3,%%g1\n" \
|
||||
" mulscc %%g1,%3,%%g1\n" \
|
||||
" mulscc %%g1,%3,%%g1\n" \
|
||||
" mulscc %%g1,%3,%%g1\n" \
|
||||
" mulscc %%g1,%3,%%g1\n" \
|
||||
" mulscc %%g1,%3,%%g1\n" \
|
||||
" mulscc %%g1,%3,%%g1\n" \
|
||||
" mulscc %%g1,%3,%%g1\n" \
|
||||
" mulscc %%g1,%3,%%g1\n" \
|
||||
" mulscc %%g1,%3,%%g1\n" \
|
||||
" mulscc %%g1,%3,%%g1\n" \
|
||||
" mulscc %%g1,%3,%%g1\n" \
|
||||
" mulscc %%g1,%3,%%g1\n" \
|
||||
" mulscc %%g1,%3,%%g1\n" \
|
||||
" mulscc %%g1,%3,%%g1\n" \
|
||||
" mulscc %%g1,0,%%g1\n" \
|
||||
" add %%g1,%%g2,%0\n" \
|
||||
" rd %%y,%1" \
|
||||
: "=r" (w1), "=r" (w0) : "%rI" (u), "r" (v) \
|
||||
: "%g1", "%g2" __AND_CLOBBER_CC)
|
||||
#define UMUL_TIME 39 /* 39 instructions */
|
||||
#endif
|
||||
#ifndef udiv_qrnnd
|
||||
#ifndef LONGLONG_STANDALONE
|
||||
#define udiv_qrnnd(q, r, n1, n0, d) \
|
||||
do { UWtype __r; \
|
||||
(q) = __MPN(udiv_qrnnd) (&__r, (n1), (n0), (d)); \
|
||||
(r) = __r; \
|
||||
} while (0)
|
||||
extern UWtype __MPN(udiv_qrnnd) _PROTO ((UWtype *, UWtype, UWtype, UWtype));
|
||||
#ifndef UDIV_TIME
|
||||
#define UDIV_TIME 140
|
||||
#endif
|
||||
#endif /* LONGLONG_STANDALONE */
|
||||
#endif /* udiv_qrnnd */
|
||||
18
mpn/sparc64/longlong.h
Normal file
18
mpn/sparc64/longlong.h
Normal file
@ -0,0 +1,18 @@
|
||||
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
|
||||
__asm__ ( \
|
||||
"addcc %r4,%5,%1\n" \
|
||||
" addccc %r6,%7,%%g0\n" \
|
||||
" addc %r2,%3,%0" \
|
||||
: "=r" (sh), "=&r" (sl) \
|
||||
: "rJ" (ah), "rI" (bh), "%rJ" (al), "rI" (bl), \
|
||||
"%rJ" ((al) >> 32), "rI" ((bl) >> 32) \
|
||||
__CLOBBER_CC)
|
||||
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
|
||||
__asm__ ( \
|
||||
"subcc %r4,%5,%1\n" \
|
||||
" subccc %r6,%7,%%g0\n" \
|
||||
" subc %r2,%3,%0" \
|
||||
: "=r" (sh), "=&r" (sl) \
|
||||
: "rJ" (ah), "rI" (bh), "rJ" (al), "rI" (bl), \
|
||||
"rJ" ((al) >> 32), "rI" ((bl) >> 32) \
|
||||
__CLOBBER_CC)
|
||||
138
mpn/x86/longlong.h
Normal file
138
mpn/x86/longlong.h
Normal file
@ -0,0 +1,138 @@
|
||||
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
|
||||
__asm__ ("addl %5,%k1\n\tadcl %3,%k0" \
|
||||
: "=r" (sh), "=&r" (sl) \
|
||||
: "0" ((USItype)(ah)), "g" ((USItype)(bh)), \
|
||||
"%1" ((USItype)(al)), "g" ((USItype)(bl)))
|
||||
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
|
||||
__asm__ ("subl %5,%k1\n\tsbbl %3,%k0" \
|
||||
: "=r" (sh), "=&r" (sl) \
|
||||
: "0" ((USItype)(ah)), "g" ((USItype)(bh)), \
|
||||
"1" ((USItype)(al)), "g" ((USItype)(bl)))
|
||||
#define umul_ppmm(w1, w0, u, v) \
|
||||
__asm__ ("mull %3" \
|
||||
: "=a" (w0), "=d" (w1) \
|
||||
: "%0" ((USItype)(u)), "rm" ((USItype)(v)))
|
||||
#define udiv_qrnnd(q, r, n1, n0, dx) /* d renamed to dx avoiding "=d" */\
|
||||
__asm__ ("divl %4" /* stringification in K&R C */ \
|
||||
: "=a" (q), "=d" (r) \
|
||||
: "0" ((USItype)(n0)), "1" ((USItype)(n1)), "rm" ((USItype)(dx)))
|
||||
|
||||
#if HAVE_HOST_CPU_i586 || HAVE_HOST_CPU_pentium || HAVE_HOST_CPU_pentiummmx
|
||||
/* Pentium bsrl takes between 10 and 72 cycles depending where the most
|
||||
significant 1 bit is, hence the use of the following alternatives. bsfl
|
||||
is slow too, between 18 and 42 depending where the least significant 1
|
||||
bit is, so let the generic count_trailing_zeros below make use of the
|
||||
count_leading_zeros here too. */
|
||||
|
||||
#if HAVE_HOST_CPU_pentiummmx && ! defined (LONGLONG_STANDALONE)
|
||||
/* The following should be a fixed 14 or 15 cycles, but possibly plus an L1
|
||||
cache miss reading from __clz_tab. For P55 it's favoured over the float
|
||||
below so as to avoid mixing MMX and x87, since the penalty for switching
|
||||
between the two is about 100 cycles.
|
||||
|
||||
The asm block sets __shift to -3 if the high 24 bits are clear, -2 for
|
||||
16, -1 for 8, or 0 otherwise. This could be written equivalently as
|
||||
follows, but as of gcc 2.95.2 it results in conditional jumps.
|
||||
|
||||
__shift = -(__n < 0x1000000);
|
||||
__shift -= (__n < 0x10000);
|
||||
__shift -= (__n < 0x100);
|
||||
|
||||
The middle two sbbl and cmpl's pair, and with luck something gcc
|
||||
generates might pair with the first cmpl and the last sbbl. The "32+1"
|
||||
constant could be folded into __clz_tab[], but it doesn't seem worth
|
||||
making a different table just for that. */
|
||||
|
||||
#define count_leading_zeros(c,n) \
|
||||
do { \
|
||||
USItype __n = (n); \
|
||||
USItype __shift; \
|
||||
__asm__ ("cmpl $0x1000000, %1\n" \
|
||||
"sbbl %0, %0\n" \
|
||||
"cmpl $0x10000, %1\n" \
|
||||
"sbbl $0, %0\n" \
|
||||
"cmpl $0x100, %1\n" \
|
||||
"sbbl $0, %0\n" \
|
||||
: "=&r" (__shift) : "r" (__n)); \
|
||||
__shift = __shift*8 + 24 + 1; \
|
||||
(c) = 32 + 1 - __shift - __clz_tab[__n >> __shift]; \
|
||||
} while (0)
|
||||
#define COUNT_LEADING_ZEROS_NEED_CLZ_TAB
|
||||
#define COUNT_LEADING_ZEROS_0 31 /* n==0 indistinguishable from n==1 */
|
||||
|
||||
#else /* ! pentiummmx || LONGLONG_STANDALONE */
|
||||
/* The following should be a fixed 14 cycles or so. Some scheduling
|
||||
opportunities should be available between the float load/store too. This
|
||||
sort of code is used in gcc 3 for __builtin_ffs (with "n&-n") and is
|
||||
apparently suggested by the Intel optimizing manual (don't know exactly
|
||||
where). gcc 2.95 or up will be best for this, so the "double" is
|
||||
correctly aligned on the stack. */
|
||||
#define count_leading_zeros(c,n) \
|
||||
do { \
|
||||
union { \
|
||||
double d; \
|
||||
unsigned a[2]; \
|
||||
} __u; \
|
||||
ASSERT ((n) != 0); \
|
||||
__u.d = (UWtype) (n); \
|
||||
(c) = 0x3FF + 31 - (__u.a[1] >> 20); \
|
||||
} while (0)
|
||||
#define COUNT_LEADING_ZEROS_0 (0x3FF + 31)
|
||||
#endif /* pentiummx */
|
||||
|
||||
#else /* ! pentium */
|
||||
|
||||
#if __GMP_GNUC_PREREQ (3,4) /* using bsrl */
|
||||
#define count_leading_zeros(count,x) count_leading_zeros_gcc_clz(count,x)
|
||||
#endif /* gcc clz */
|
||||
|
||||
/* On P6, gcc prior to 3.0 generates a partial register stall for
|
||||
__cbtmp^31, due to using "xorb $31" instead of "xorl $31", the former
|
||||
being 1 code byte smaller. "31-__cbtmp" is a workaround, probably at the
|
||||
cost of one extra instruction. Do this for "i386" too, since that means
|
||||
generic x86. */
|
||||
#if ! defined (count_leading_zeros) && __GNUC__ < 3 \
|
||||
&& (HAVE_HOST_CPU_i386 \
|
||||
|| HAVE_HOST_CPU_i686 \
|
||||
|| HAVE_HOST_CPU_pentiumpro \
|
||||
|| HAVE_HOST_CPU_pentium2 \
|
||||
|| HAVE_HOST_CPU_pentium3)
|
||||
#define count_leading_zeros(count, x) \
|
||||
do { \
|
||||
USItype __cbtmp; \
|
||||
ASSERT ((x) != 0); \
|
||||
__asm__ ("bsrl %1,%0" : "=r" (__cbtmp) : "rm" ((USItype)(x))); \
|
||||
(count) = 31 - __cbtmp; \
|
||||
} while (0)
|
||||
#endif /* gcc<3 asm bsrl */
|
||||
|
||||
#ifndef count_leading_zeros
|
||||
#define count_leading_zeros(count, x) \
|
||||
do { \
|
||||
USItype __cbtmp; \
|
||||
ASSERT ((x) != 0); \
|
||||
__asm__ ("bsrl %1,%0" : "=r" (__cbtmp) : "rm" ((USItype)(x))); \
|
||||
(count) = __cbtmp ^ 31; \
|
||||
} while (0)
|
||||
#endif /* asm bsrl */
|
||||
|
||||
#if __GMP_GNUC_PREREQ (3,4) /* using bsfl */
|
||||
#define count_trailing_zeros(count,x) count_trailing_zeros_gcc_ctz(count,x)
|
||||
#endif /* gcc ctz */
|
||||
|
||||
#ifndef count_trailing_zeros
|
||||
#define count_trailing_zeros(count, x) \
|
||||
do { \
|
||||
ASSERT ((x) != 0); \
|
||||
__asm__ ("bsfl %1,%0" : "=r" (count) : "rm" ((USItype)(x))); \
|
||||
} while (0)
|
||||
#endif /* asm bsfl */
|
||||
|
||||
#endif /* ! pentium */
|
||||
|
||||
#ifndef UMUL_TIME
|
||||
#define UMUL_TIME 10
|
||||
#endif
|
||||
#ifndef UDIV_TIME
|
||||
#define UDIV_TIME 40
|
||||
#endif
|
||||
33
mpn/x86_64/longlong.h
Normal file
33
mpn/x86_64/longlong.h
Normal file
@ -0,0 +1,33 @@
|
||||
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
|
||||
__asm__ ("addq %5,%q1\n\tadcq %3,%q0" \
|
||||
: "=r" (sh), "=&r" (sl) \
|
||||
: "0" ((UDItype)(ah)), "rme" ((UDItype)(bh)), \
|
||||
"%1" ((UDItype)(al)), "rme" ((UDItype)(bl)))
|
||||
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
|
||||
__asm__ ("subq %5,%q1\n\tsbbq %3,%q0" \
|
||||
: "=r" (sh), "=&r" (sl) \
|
||||
: "0" ((UDItype)(ah)), "rme" ((UDItype)(bh)), \
|
||||
"1" ((UDItype)(al)), "rme" ((UDItype)(bl)))
|
||||
#define umul_ppmm(w1, w0, u, v) \
|
||||
__asm__ ("mulq %3" \
|
||||
: "=a" (w0), "=d" (w1) \
|
||||
: "%0" ((UDItype)(u)), "rm" ((UDItype)(v)))
|
||||
#define udiv_qrnnd(q, r, n1, n0, dx) /* d renamed to dx avoiding "=d" */\
|
||||
__asm__ ("divq %4" /* stringification in K&R C */ \
|
||||
: "=a" (q), "=d" (r) \
|
||||
: "0" ((UDItype)(n0)), "1" ((UDItype)(n1)), "rm" ((UDItype)(dx)))
|
||||
/* bsrq destination must be a 64-bit register, hence UDItype for __cbtmp. */
|
||||
#define count_leading_zeros(count, x) \
|
||||
do { \
|
||||
UDItype __cbtmp; \
|
||||
ASSERT ((x) != 0); \
|
||||
__asm__ ("bsrq %1,%0" : "=r" (__cbtmp) : "rm" ((UDItype)(x))); \
|
||||
(count) = __cbtmp ^ 63; \
|
||||
} while (0)
|
||||
/* bsfq destination must be a 64-bit register, "%q0" forces this in case
|
||||
count is only an int. */
|
||||
#define count_trailing_zeros(count, x) \
|
||||
do { \
|
||||
ASSERT ((x) != 0); \
|
||||
__asm__ ("bsfq %1,%q0" : "=r" (count) : "rm" ((UDItype)(x))); \
|
||||
} while (0)
|
||||
Loading…
Reference in New Issue
Block a user