Tuning for ARM.

This commit is contained in:
(no author) 2010-04-02 07:15:12 +00:00
parent e17acf85f1
commit 366975ecb6

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@ -25,29 +25,23 @@ MA 02110-1301, USA. */
/* 1.2 GHz ARM Feroceon */
/* Generated by tuneup.c, 2009-06-02, gcc 4.1 */
/* Generated by tuneup.c, 2010-04-02, gcc 4.3 */
#define MUL_KARATSUBA_THRESHOLD 36
#define MUL_TOOM3_THRESHOLD 125
#define MUL_TOOM4_THRESHOLD 280
#define MUL_TOOM7_THRESHOLD 306
#define MUL_TOOM4_THRESHOLD 178
#define MUL_TOOM8H_THRESHOLD 414
#define SQR_BASECASE_THRESHOLD 12
#define SQR_KARATSUBA_THRESHOLD 80
#define SQR_TOOM3_THRESHOLD 197
#define SQR_TOOM4_THRESHOLD 490
#define SQR_TOOM7_THRESHOLD 552
#define SQR_KARATSUBA_THRESHOLD 82
#define SQR_TOOM3_THRESHOLD 138
#define SQR_TOOM4_THRESHOLD 348
#define SQR_TOOM8_THRESHOLD 381
#define MULLOW_BASECASE_THRESHOLD 0 /* always */
#define MULLOW_DC_THRESHOLD 140
#define MULLOW_MUL_N_THRESHOLD 517
#define POWM_THRESHOLD 170
#define DIV_SB_PREINV_THRESHOLD 0 /* preinv always */
#define DIV_DC_THRESHOLD 134
#define POWM_THRESHOLD 236
#define GCD_ACCEL_THRESHOLD 21
#define GCDEXT_THRESHOLD 8
#define GCD_ACCEL_THRESHOLD 6
#define GCDEXT_THRESHOLD 0 /* always */
#define JACOBI_BASE_METHOD 2
#define DIVREM_1_NORM_THRESHOLD 0 /* preinv always */
@ -59,18 +53,48 @@ MA 02110-1301, USA. */
#define DIVREM_2_THRESHOLD 0 /* preinv always */
#define DIVEXACT_1_THRESHOLD 0 /* always */
#define MODEXACT_1_ODD_THRESHOLD 0 /* always */
#define MOD_1_1_THRESHOLD 7
#define MOD_1_2_THRESHOLD 996
#define MOD_1_3_THRESHOLD 996
#define DIVREM_HENSEL_QR_1_THRESHOLD 10
#define RSH_DIVREM_HENSEL_QR_1_THRESHOLD 996
#define DIVREM_EUCLID_HENSEL_THRESHOLD 40
#define GET_STR_DC_THRESHOLD 25
#define GET_STR_PRECOMPUTE_THRESHOLD 43
#define SET_STR_THRESHOLD 7764
#define ROOTREM_THRESHOLD 6
#define MUL_FFT_TABLE { 400, 1120, 1408, 3584, 10240, 40960, 163840, 655360, 0 }
#define GET_STR_DC_THRESHOLD 17
#define GET_STR_PRECOMPUTE_THRESHOLD 30
#define SET_STR_DC_THRESHOLD 12643
#define SET_STR_PRECOMPUTE_THRESHOLD 12643
#define MUL_FFT_TABLE { 400, 1056, 1408, 3584, 10240, 40960, 163840, 655360, 0 }
#define MUL_FFT_MODF_THRESHOLD 416
#define MUL_FFT_THRESHOLD 7168
#define MUL_FFT_FULL_THRESHOLD 1664
#define SQR_FFT_TABLE { 464, 1120, 1408, 3584, 10240, 40960, 163840, 655360, 0 }
#define SQR_FFT_MODF_THRESHOLD 312
#define SQR_FFT_THRESHOLD 3840
#define SQR_FFT_TABLE { 432, 1120, 1408, 3584, 10240, 40960, 163840, 655360, 0 }
#define SQR_FFT_MODF_THRESHOLD 344
#define SQR_FFT_FULL_THRESHOLD 1664
/* Tuneup completed successfully, took 105 seconds */
#define MULLOW_BASECASE_THRESHOLD 0 /* always */
#define MULLOW_DC_THRESHOLD 123
#define MULLOW_MUL_THRESHOLD 2464
#define MULHIGH_BASECASE_THRESHOLD 5
#define MULHIGH_DC_THRESHOLD 122
#define MULHIGH_MUL_THRESHOLD 2664
#define MULMOD_2EXPM1_THRESHOLD 28
#define FAC_UI_THRESHOLD 6838
#define DC_DIV_QR_THRESHOLD 132
#define DC_DIVAPPR_Q_N_THRESHOLD 706
#define INV_DIV_QR_THRESHOLD 1387
#define INV_DIVAPPR_Q_N_THRESHOLD 706
#define DC_DIV_Q_THRESHOLD 734
#define INV_DIV_Q_THRESHOLD 2397
#define DC_DIVAPPR_Q_THRESHOLD 706
#define INV_DIVAPPR_Q_THRESHOLD 9198
#define DC_BDIV_QR_THRESHOLD 140
#define DC_BDIV_Q_THRESHOLD 386
/* Tuneup completed successfully, took 596 seconds */