70 lines
2.9 KiB
Plaintext
70 lines
2.9 KiB
Plaintext
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Copyright 1999, 2001, 2002, 2004 Free Software Foundation, Inc.
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This file is part of the GNU MP Library.
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The GNU MP Library is free software; you can redistribute it and/or modify
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it under the terms of the GNU Lesser General Public License as published by
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the Free Software Foundation; either version 2.1 of the License, or (at your
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option) any later version.
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The GNU MP Library is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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License for more details.
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You should have received a copy of the GNU Lesser General Public License
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along with the GNU MP Library; see the file COPYING.LIB. If not, write to
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the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
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02110-1301, USA.
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This directory contains mpn functions for 64-bit PA-RISC 2.0.
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PIPELINE SUMMARY
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The PA8x00 processors have an orthogonal 4-way out-of-order pipeline. Each
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cycle two ALU operations and two MEM operations can issue, but just one of the
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MEM operations may be a store. The two ALU operations can be almost any
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combination of non-memory operations. Unlike every other processor, integer
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and fp operations are completely equal here; they both count as just ALU
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operations.
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Unfortunately, some operations cause hickups in the pipeline. Combining
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carry-consuming operations like ADD,DC with operations that does not set carry
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like ADD,L cause long delays. Skip operations also seem to cause hickups. If
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several ADD,DC are issued consecutively, or if plain carry-generating ADD feed
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ADD,DC, stalling does not occur. We can effectively issue two ADD,DC
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operations/cycle.
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Latency scheduling is not as important as making sure to have a mix of ALU and
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MEM operations, but for full pipeline utilization, it is still a good idea to
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do some amount of latency scheduling.
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Like for all other processors, RAW memory scheduling is critically important.
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Since integer multiplication takes place in the floating-point unit, the GMP
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code needs to handle this problem frequently.
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STATUS
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* mpn_lshift and mpn_rshift run at 1.5 cycles/limb on PA8000 and at 1.0
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cycles/limb on PA8500. With latency scheduling, the numbers could
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probably be improved to 1.0 cycles/limb for all PA8x00 chips.
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* mpn_add_n and mpn_sub_n run at 2.0 cycles/limb on PA8000 and at about
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1.6875 cycles/limb on PA8500. With latency scheduling, this could
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probably be improved to get close to 1.5 cycles/limb. A problem is the
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stalling of carry-inputting instructions after instructions that do not
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write to carry.
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* mpn_mul_1, mpn_addmul_1, and mpn_submul_1 run at between 5.625 and 6.375
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on PA8500 and later, and about a cycle/limb slower on older chips. The
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code uses ADD,DC for adjacent limbs, and relies heavily on reordering.
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REFERENCES
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Hewlett Packard, "64-Bit Runtime Architecture for PA-RISC 2.0", version 3.3,
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October 1997.
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