388 lines
7.7 KiB
NASM
388 lines
7.7 KiB
NASM
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dnl Alpha ev6 nails mpn_submul_1.
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dnl Copyright 2002, 2005, 2006 Free Software Foundation, Inc.
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dnl
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dnl This file is part of the GNU MP Library.
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dnl
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dnl The GNU MP Library is free software; you can redistribute it and/or
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dnl modify it under the terms of the GNU Lesser General Public License as
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dnl published by the Free Software Foundation; either version 2.1 of the
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dnl License, or (at your option) any later version.
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dnl
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dnl The GNU MP Library is distributed in the hope that it will be useful,
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dnl but WITHOUT ANY WARRANTY; without even the implied warranty of
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dnl MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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dnl Lesser General Public License for more details.
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dnl
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dnl You should have received a copy of the GNU Lesser General Public
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dnl License along with the GNU MP Library; see the file COPYING.LIB. If
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dnl not, write to the Free Software Foundation, Inc., 51 Franklin Street,
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dnl Fifth Floor, Boston, MA 02110-1301, USA.
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include(`../config.m4')
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C cycles/limb
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C EV4: 42
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C EV5: 18
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C EV6: 4
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C TODO
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C * Reroll loop for 3.75 c/l with current 4-way unrulling.
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C * The loop is overscheduled wrt loads and wrt multiplies, in particular
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C umulh.
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C * Use FP loop count and multiple exit points, that would simpily feed-in lp0
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C and would work since the loop structure is really regular.
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C INPUT PARAMETERS
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define(`rp',`r16')
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define(`up',`r17')
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define(`n', `r18')
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define(`vl0',`r19')
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define(`numb_mask',`r6')
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define(`m0a',`r0')
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define(`m0b',`r1')
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define(`m1a',`r2')
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define(`m1b',`r3')
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define(`m2a',`r20')
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define(`m2b',`r21')
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define(`m3a',`r22')
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define(`m3b',`r23')
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define(`acc0',`r25')
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define(`acc1',`r27')
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define(`ul0',`r4')
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define(`ul1',`r5')
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define(`ul2',`r4')
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define(`ul3',`r5')
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define(`rl0',`r24')
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define(`rl1',`r24')
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define(`rl2',`r24')
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define(`rl3',`r24')
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define(`t0',`r7')
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define(`t1',`r8')
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define(`NAIL_BITS',`GMP_NAIL_BITS')
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define(`NUMB_BITS',`GMP_NUMB_BITS')
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dnl This declaration is munged by configure
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NAILS_SUPPORT(2-63)
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ASM_START()
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PROLOGUE(mpn_submul_1)
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sll vl0, NAIL_BITS, vl0
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lda numb_mask, -1(r31)
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srl numb_mask, NAIL_BITS, numb_mask
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and n, 3, r25
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cmpeq r25, 1, r21
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bne r21, L(1m4)
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cmpeq r25, 2, r21
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bne r21, L(2m4)
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beq r25, L(0m4)
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L(3m4): ldq ul3, 0(up)
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lda n, -4(n)
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ldq ul0, 8(up)
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mulq vl0, ul3, m3a
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umulh vl0, ul3, m3b
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ldq ul1, 16(up)
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lda up, 24(up)
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lda rp, -8(rp)
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mulq vl0, ul0, m0a
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umulh vl0, ul0, m0b
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bge n, L(ge3)
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mulq vl0, ul1, m1a
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umulh vl0, ul1, m1b
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ldq rl3, 8(rp)
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srl m3a,NAIL_BITS, t0
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addq t0, r31, acc1
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subq rl3, acc1, acc1
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ldq rl0, 16(rp)
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srl m0a,NAIL_BITS, t0
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addq t0, m3b, acc0
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sra acc1,NUMB_BITS, t1
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br r31, L(ta3)
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L(ge3): ldq ul2, 0(up)
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mulq vl0, ul1, m1a
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umulh vl0, ul1, m1b
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ldq rl3, 8(rp)
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srl m3a,NAIL_BITS, t0
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ldq ul3, 8(up)
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lda n, -4(n)
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mulq vl0, ul2, m2a
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addq t0, r31, acc1
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umulh vl0, ul2, m2b
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subq rl3, acc1, acc1
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ldq rl0, 16(rp)
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srl m0a,NAIL_BITS, t0
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ldq ul0, 16(up)
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mulq vl0, ul3, m3a
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addq t0, m3b, acc0
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sra acc1,NUMB_BITS, t1
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br r31, L(el3)
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L(0m4): lda n, -8(n)
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ldq ul2, 0(up)
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ldq ul3, 8(up)
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mulq vl0, ul2, m2a
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umulh vl0, ul2, m2b
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ldq ul0, 16(up)
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mulq vl0, ul3, m3a
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umulh vl0, ul3, m3b
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ldq ul1, 24(up)
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lda up, 32(up)
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mulq vl0, ul0, m0a
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umulh vl0, ul0, m0b
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bge n, L(ge4)
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ldq rl2, 0(rp)
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srl m2a,NAIL_BITS, t0
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mulq vl0, ul1, m1a
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addq t0, r31, acc0
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umulh vl0, ul1, m1b
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subq rl2, acc0, acc0
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ldq rl3, 8(rp)
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srl m3a,NAIL_BITS, t0
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addq t0, m2b, acc1
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sra acc0,NUMB_BITS, t1
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br r31, L(ta4)
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L(ge4): ldq rl2, 0(rp)
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srl m2a,NAIL_BITS, t0
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ldq ul2, 0(up)
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mulq vl0, ul1, m1a
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addq t0, r31, acc0
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umulh vl0, ul1, m1b
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subq rl2, acc0, acc0
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ldq rl3, 8(rp)
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srl m3a,NAIL_BITS, t0
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ldq ul3, 8(up)
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lda n, -4(n)
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mulq vl0, ul2, m2a
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addq t0, m2b, acc1
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sra acc0,NUMB_BITS, t1
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br r31, L(el0)
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L(2m4): lda n, -4(n)
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ldq ul0, 0(up)
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ldq ul1, 8(up)
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lda up, 16(up)
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lda rp, -16(rp)
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mulq vl0, ul0, m0a
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umulh vl0, ul0, m0b
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bge n, L(ge2)
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mulq vl0, ul1, m1a
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umulh vl0, ul1, m1b
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ldq rl0, 16(rp)
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srl m0a,NAIL_BITS, t0
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addq t0, r31, acc0
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subq rl0, acc0, acc0
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ldq rl1, 24(rp)
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srl m1a,NAIL_BITS, t0
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addq t0, m0b, acc1
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sra acc0,NUMB_BITS, t1
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br r31, L(ta2)
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L(ge2): ldq ul2, 0(up)
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mulq vl0, ul1, m1a
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umulh vl0, ul1, m1b
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ldq ul3, 8(up)
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lda n, -4(n)
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mulq vl0, ul2, m2a
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umulh vl0, ul2, m2b
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ldq rl0, 16(rp)
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srl m0a,NAIL_BITS, t0
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ldq ul0, 16(up)
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mulq vl0, ul3, m3a
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addq t0, r31, acc0
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umulh vl0, ul3, m3b
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subq rl0, acc0, acc0
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ldq rl1, 24(rp)
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srl m1a,NAIL_BITS, t0
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ldq ul1, 24(up)
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lda up, 32(up)
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lda rp, 32(rp)
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mulq vl0, ul0, m0a
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addq t0, m0b, acc1
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sra acc0,NUMB_BITS, t1
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bge n, L(el2)
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br r31, L(ta6)
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L(1m4): lda n, -4(n)
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ldq ul1, 0(up)
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lda up, 8(up)
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lda rp, -24(rp)
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bge n, L(ge1)
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mulq vl0, ul1, m1a
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umulh vl0, ul1, m1b
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ldq rl1, 24(rp)
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srl m1a,NAIL_BITS, t0
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subq rl1, t0, acc1
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and acc1,numb_mask, r28
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sra acc1,NUMB_BITS, t1
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stq r28, 24(rp)
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subq m1b, t1, r0
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ret r31, (r26), 1
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L(ge1): ldq ul2, 0(up)
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mulq vl0, ul1, m1a
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umulh vl0, ul1, m1b
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ldq ul3, 8(up)
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lda n, -4(n)
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mulq vl0, ul2, m2a
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umulh vl0, ul2, m2b
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ldq ul0, 16(up)
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mulq vl0, ul3, m3a
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umulh vl0, ul3, m3b
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ldq rl1, 24(rp)
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srl m1a,NAIL_BITS, t0
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ldq ul1, 24(up)
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lda up, 32(up)
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lda rp, 32(rp)
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mulq vl0, ul0, m0a
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addq t0, r31, acc1
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umulh vl0, ul0, m0b
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subq rl1, acc1, acc1
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ldq rl2, 0(rp)
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srl m2a,NAIL_BITS, t0
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mulq vl0, ul1, m1a
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addq t0, m1b, acc0
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sra acc1,NUMB_BITS, t1
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blt n, L(ta5)
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L(ge5): ldq ul2, 0(up)
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br r31, L(el1)
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ALIGN(16)
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L(top): mulq vl0, ul0, m0a C U1
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addq t0, m0b, acc1 C L0
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sra acc0,NUMB_BITS, t1 C U0
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stq r28, -24(rp) C L1
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C
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L(el2): umulh vl0, ul0, m0b C U1
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and acc0,numb_mask, r28 C L0
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subq rl1, acc1, acc1 C U0
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ldq rl2, 0(rp) C L1
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C
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unop C U1
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addq t1, acc1, acc1 C L0
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srl m2a,NAIL_BITS, t0 C U0
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ldq ul2, 0(up) C L1
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C
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mulq vl0, ul1, m1a C U1
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addq t0, m1b, acc0 C L0
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sra acc1,NUMB_BITS, t1 C U0
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stq r28, -16(rp) C L1
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C
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L(el1): umulh vl0, ul1, m1b C U1
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and acc1,numb_mask, r28 C L0
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subq rl2, acc0, acc0 C U0
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ldq rl3, 8(rp) C L1
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C
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lda n, -4(n) C L1
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addq t1, acc0, acc0 C L0
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srl m3a,NAIL_BITS, t0 C U0
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ldq ul3, 8(up) C L1
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C
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mulq vl0, ul2, m2a C U1
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addq t0, m2b, acc1 C L0
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sra acc0,NUMB_BITS, t1 C U0
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stq r28, -8(rp) C L1
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C
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L(el0): umulh vl0, ul2, m2b C U1
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and acc0,numb_mask, r28 C L0
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subq rl3, acc1, acc1 C U0
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ldq rl0, 16(rp) C L1
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C
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unop C U1
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addq t1, acc1, acc1 C L0
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srl m0a,NAIL_BITS, t0 C U0
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ldq ul0, 16(up) C L1
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C
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mulq vl0, ul3, m3a C U1
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addq t0, m3b, acc0 C L0
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sra acc1,NUMB_BITS, t1 C U0
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stq r28, 0(rp) C L1
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C
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L(el3): umulh vl0, ul3, m3b C U1
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and acc1,numb_mask, r28 C L0
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subq rl0, acc0, acc0 C U0
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ldq rl1, 24(rp) C L1
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C
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unop C U1
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addq t1, acc0, acc0 C L0
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srl m1a,NAIL_BITS, t0 C U0
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ldq ul1, 24(up) C L1
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C
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lda up, 32(up) C L0
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unop C U1
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lda rp, 32(rp) C L1
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bge n, L(top) C U0
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L(end): mulq vl0, ul0, m0a
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addq t0, m0b, acc1
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sra acc0,NUMB_BITS, t1
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stq r28, -24(rp)
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L(ta6): umulh vl0, ul0, m0b
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and acc0,numb_mask, r28
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subq rl1, acc1, acc1
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ldq rl2, 0(rp)
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addq t1, acc1, acc1
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srl m2a,NAIL_BITS, t0
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mulq vl0, ul1, m1a
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addq t0, m1b, acc0
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||
|
|
sra acc1,NUMB_BITS, t1
|
||
|
|
stq r28, -16(rp)
|
||
|
|
L(ta5): umulh vl0, ul1, m1b
|
||
|
|
and acc1,numb_mask, r28
|
||
|
|
subq rl2, acc0, acc0
|
||
|
|
ldq rl3, 8(rp)
|
||
|
|
addq t1, acc0, acc0
|
||
|
|
srl m3a,NAIL_BITS, t0
|
||
|
|
addq t0, m2b, acc1
|
||
|
|
sra acc0,NUMB_BITS, t1
|
||
|
|
stq r28, -8(rp)
|
||
|
|
unop
|
||
|
|
ALIGN(16)
|
||
|
|
L(ta4): and acc0,numb_mask, r28
|
||
|
|
subq rl3, acc1, acc1
|
||
|
|
ldq rl0, 16(rp)
|
||
|
|
addq t1, acc1, acc1
|
||
|
|
srl m0a,NAIL_BITS, t0
|
||
|
|
addq t0, m3b, acc0
|
||
|
|
sra acc1,NUMB_BITS, t1
|
||
|
|
stq r28, 0(rp)
|
||
|
|
unop
|
||
|
|
ALIGN(16)
|
||
|
|
L(ta3): and acc1,numb_mask, r28
|
||
|
|
subq rl0, acc0, acc0
|
||
|
|
ldq rl1, 24(rp)
|
||
|
|
addq t1, acc0, acc0
|
||
|
|
srl m1a,NAIL_BITS, t0
|
||
|
|
addq t0, m0b, acc1
|
||
|
|
sra acc0,NUMB_BITS, t1
|
||
|
|
stq r28, 8(rp)
|
||
|
|
unop
|
||
|
|
ALIGN(16)
|
||
|
|
L(ta2): and acc0,numb_mask, r28
|
||
|
|
subq rl1, acc1, acc1
|
||
|
|
addq t1, acc1, acc1
|
||
|
|
sra acc1,NUMB_BITS, t1
|
||
|
|
stq r28, 16(rp)
|
||
|
|
and acc1,numb_mask, r28
|
||
|
|
subq m1b, t1, r0
|
||
|
|
stq r28, 24(rp)
|
||
|
|
ret r31, (r26), 1
|
||
|
|
EPILOGUE()
|
||
|
|
ASM_END()
|