299 lines
7.9 KiB
Plaintext
299 lines
7.9 KiB
Plaintext
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#
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# x86 register and target modifier recognition
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#
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# Copyright (C) 2002-2007 Peter Johnson
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions
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# are met:
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# 1. Redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer.
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# 2. Redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution.
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#
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# THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND OTHER CONTRIBUTORS ``AS IS''
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# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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# ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR OTHER CONTRIBUTORS BE
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# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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# POSSIBILITY OF SUCH DAMAGE.
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%{
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#include <util.h>
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RCSID("$Id: x86regtmod.gperf 2062 2008-04-12 01:34:30Z peter $");
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#include <ctype.h>
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#include <libyasm.h>
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#include <libyasm/phash.h>
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#include "modules/arch/x86/x86arch.h"
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enum regtmod_type {
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REG = 1,
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REGGROUP,
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SEGREG,
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TARGETMOD
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};
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%}
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%ignore-case
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%language=ANSI-C
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%compare-strncmp
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%readonly-tables
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%enum
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%struct-type
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%define hash-function-name regtmod_hash
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%define lookup-function-name regtmod_find
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struct regtmod_parse_data {
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const char *name;
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unsigned int type:8; /* regtmod_type */
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/* REG: register size
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* SEGREG: prefix encoding
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* Others: 0
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*/
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unsigned int size_prefix:8;
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/* REG: register index
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* REGGROUP: register group type
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* SEGREG: register encoding
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* TARGETMOD: target modifier
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*/
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unsigned int data:8;
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/* REG: required bits setting
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* SEGREG: BITS in which the segment is ignored
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* Others: 0
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*/
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unsigned int bits:8;
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};
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%%
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#
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# control, debug, and test registers
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#
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cr0, REG, X86_CRREG, 0, 0
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cr2, REG, X86_CRREG, 2, 0
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cr3, REG, X86_CRREG, 3, 0
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cr4, REG, X86_CRREG, 4, 0
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cr8, REG, X86_CRREG, 8, 64
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#
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dr0, REG, X86_DRREG, 0, 0
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dr1, REG, X86_DRREG, 1, 0
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dr2, REG, X86_DRREG, 2, 0
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dr3, REG, X86_DRREG, 3, 0
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dr4, REG, X86_DRREG, 4, 0
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dr5, REG, X86_DRREG, 5, 0
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dr6, REG, X86_DRREG, 6, 0
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dr7, REG, X86_DRREG, 7, 0
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#
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tr0, REG, X86_TRREG, 0, 0
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tr1, REG, X86_TRREG, 1, 0
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tr2, REG, X86_TRREG, 2, 0
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tr3, REG, X86_TRREG, 3, 0
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tr4, REG, X86_TRREG, 4, 0
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tr5, REG, X86_TRREG, 5, 0
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tr6, REG, X86_TRREG, 6, 0
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tr7, REG, X86_TRREG, 7, 0
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#
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# floating point, MMX, and SSE/SSE2 registers
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#
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st0, REG, X86_FPUREG, 0, 0
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st1, REG, X86_FPUREG, 1, 0
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st2, REG, X86_FPUREG, 2, 0
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st3, REG, X86_FPUREG, 3, 0
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st4, REG, X86_FPUREG, 4, 0
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st5, REG, X86_FPUREG, 5, 0
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st6, REG, X86_FPUREG, 6, 0
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st7, REG, X86_FPUREG, 7, 0
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#
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mm0, REG, X86_MMXREG, 0, 0
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mm1, REG, X86_MMXREG, 1, 0
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mm2, REG, X86_MMXREG, 2, 0
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mm3, REG, X86_MMXREG, 3, 0
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mm4, REG, X86_MMXREG, 4, 0
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mm5, REG, X86_MMXREG, 5, 0
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mm6, REG, X86_MMXREG, 6, 0
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mm7, REG, X86_MMXREG, 7, 0
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#
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xmm0, REG, X86_XMMREG, 0, 0
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xmm1, REG, X86_XMMREG, 1, 0
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xmm2, REG, X86_XMMREG, 2, 0
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xmm3, REG, X86_XMMREG, 3, 0
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xmm4, REG, X86_XMMREG, 4, 0
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xmm5, REG, X86_XMMREG, 5, 0
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xmm6, REG, X86_XMMREG, 6, 0
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xmm7, REG, X86_XMMREG, 7, 0
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xmm8, REG, X86_XMMREG, 8, 64
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xmm9, REG, X86_XMMREG, 9, 64
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xmm10, REG, X86_XMMREG, 10, 64
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xmm11, REG, X86_XMMREG, 11, 64
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xmm12, REG, X86_XMMREG, 12, 64
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xmm13, REG, X86_XMMREG, 13, 64
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xmm14, REG, X86_XMMREG, 14, 64
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xmm15, REG, X86_XMMREG, 15, 64
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# AVX registers
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ymm0, REG, X86_YMMREG, 0, 0
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ymm1, REG, X86_YMMREG, 1, 0
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ymm2, REG, X86_YMMREG, 2, 0
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ymm3, REG, X86_YMMREG, 3, 0
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ymm4, REG, X86_YMMREG, 4, 0
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ymm5, REG, X86_YMMREG, 5, 0
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ymm6, REG, X86_YMMREG, 6, 0
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ymm7, REG, X86_YMMREG, 7, 0
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ymm8, REG, X86_YMMREG, 8, 64
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ymm9, REG, X86_YMMREG, 9, 64
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ymm10, REG, X86_YMMREG, 10, 64
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ymm11, REG, X86_YMMREG, 11, 64
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ymm12, REG, X86_YMMREG, 12, 64
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ymm13, REG, X86_YMMREG, 13, 64
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ymm14, REG, X86_YMMREG, 14, 64
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ymm15, REG, X86_YMMREG, 15, 64
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#
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# integer registers
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#
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rax, REG, X86_REG64, 0, 64
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rcx, REG, X86_REG64, 1, 64
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rdx, REG, X86_REG64, 2, 64
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rbx, REG, X86_REG64, 3, 64
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rsp, REG, X86_REG64, 4, 64
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rbp, REG, X86_REG64, 5, 64
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rsi, REG, X86_REG64, 6, 64
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rdi, REG, X86_REG64, 7, 64
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r8, REG, X86_REG64, 8, 64
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r9, REG, X86_REG64, 9, 64
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r10, REG, X86_REG64, 10, 64
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r11, REG, X86_REG64, 11, 64
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r12, REG, X86_REG64, 12, 64
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r13, REG, X86_REG64, 13, 64
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r14, REG, X86_REG64, 14, 64
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r15, REG, X86_REG64, 15, 64
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#
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eax, REG, X86_REG32, 0, 0
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ecx, REG, X86_REG32, 1, 0
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edx, REG, X86_REG32, 2, 0
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ebx, REG, X86_REG32, 3, 0
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esp, REG, X86_REG32, 4, 0
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ebp, REG, X86_REG32, 5, 0
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esi, REG, X86_REG32, 6, 0
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edi, REG, X86_REG32, 7, 0
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r8d, REG, X86_REG32, 8, 64
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r9d, REG, X86_REG32, 9, 64
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r10d, REG, X86_REG32, 10, 64
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r11d, REG, X86_REG32, 11, 64
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r12d, REG, X86_REG32, 12, 64
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r13d, REG, X86_REG32, 13, 64
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r14d, REG, X86_REG32, 14, 64
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r15d, REG, X86_REG32, 15, 64
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#
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ax, REG, X86_REG16, 0, 0
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cx, REG, X86_REG16, 1, 0
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dx, REG, X86_REG16, 2, 0
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bx, REG, X86_REG16, 3, 0
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sp, REG, X86_REG16, 4, 0
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bp, REG, X86_REG16, 5, 0
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si, REG, X86_REG16, 6, 0
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di, REG, X86_REG16, 7, 0
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r8w, REG, X86_REG16, 8, 64
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r9w, REG, X86_REG16, 9, 64
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r10w, REG, X86_REG16, 10, 64
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r11w, REG, X86_REG16, 11, 64
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r12w, REG, X86_REG16, 12, 64
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r13w, REG, X86_REG16, 13, 64
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r14w, REG, X86_REG16, 14, 64
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r15w, REG, X86_REG16, 15, 64
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#
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al, REG, X86_REG8, 0, 0
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cl, REG, X86_REG8, 1, 0
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dl, REG, X86_REG8, 2, 0
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bl, REG, X86_REG8, 3, 0
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ah, REG, X86_REG8, 4, 0
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ch, REG, X86_REG8, 5, 0
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dh, REG, X86_REG8, 6, 0
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bh, REG, X86_REG8, 7, 0
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r8b, REG, X86_REG8, 8, 64
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r9b, REG, X86_REG8, 9, 64
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r10b, REG, X86_REG8, 10, 64
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r11b, REG, X86_REG8, 11, 64
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r12b, REG, X86_REG8, 12, 64
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r13b, REG, X86_REG8, 13, 64
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r14b, REG, X86_REG8, 14, 64
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r15b, REG, X86_REG8, 15, 64
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#
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spl, REG, X86_REG8X, 4, 64
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bpl, REG, X86_REG8X, 5, 64
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sil, REG, X86_REG8X, 6, 64
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dil, REG, X86_REG8X, 7, 64
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#
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rip, REG, X86_RIP, 0, 64
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#
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# floating point, MMX, and SSE/SSE2 registers
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#
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st, REGGROUP, 0, X86_FPUREG, 0
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mm, REGGROUP, 0, X86_MMXREG, 0
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xmm, REGGROUP, 0, X86_XMMREG, 0
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ymm, REGGROUP, 0, X86_YMMREG, 0
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#
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# segment registers
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#
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es, SEGREG, 0x26, 0x00, 64
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cs, SEGREG, 0x2e, 0x01, 0
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ss, SEGREG, 0x36, 0x02, 64
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ds, SEGREG, 0x3e, 0x03, 64
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fs, SEGREG, 0x64, 0x04, 0
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gs, SEGREG, 0x65, 0x05, 0
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#
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# target modifiers
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#
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near, TARGETMOD, 0, X86_NEAR, 0
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short, TARGETMOD, 0, X86_SHORT, 0
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far, TARGETMOD, 0, X86_FAR, 0
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to, TARGETMOD, 0, X86_TO, 0
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%%
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yasm_arch_regtmod
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yasm_x86__parse_check_regtmod(yasm_arch *arch, const char *id, size_t id_len,
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uintptr_t *data)
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{
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yasm_arch_x86 *arch_x86 = (yasm_arch_x86 *)arch;
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/*@null@*/ const struct regtmod_parse_data *pdata;
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size_t i;
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static char lcaseid[8];
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unsigned int bits;
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yasm_arch_regtmod type;
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if (id_len > 7)
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return YASM_ARCH_NOTREGTMOD;
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for (i=0; i<id_len; i++)
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lcaseid[i] = tolower(id[i]);
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lcaseid[id_len] = '\0';
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pdata = regtmod_find(lcaseid, id_len);
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if (!pdata)
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return YASM_ARCH_NOTREGTMOD;
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type = (yasm_arch_regtmod)pdata->type;
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bits = pdata->bits;
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if (type == YASM_ARCH_REG && bits != 0 && arch_x86->mode_bits != bits) {
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yasm_warn_set(YASM_WARN_GENERAL,
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N_("`%s' is a register in %u-bit mode"), id, bits);
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return YASM_ARCH_NOTREGTMOD;
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}
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if (type == YASM_ARCH_SEGREG && bits != 0 && arch_x86->mode_bits == bits) {
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yasm_warn_set(YASM_WARN_GENERAL,
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N_("`%s' segment register ignored in %u-bit mode"), id,
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bits);
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}
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if (type == YASM_ARCH_SEGREG)
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*data = (pdata->size_prefix<<8) | pdata->data;
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else
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*data = pdata->size_prefix | pdata->data;
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return type;
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}
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