52 lines
1.8 KiB
Plaintext
52 lines
1.8 KiB
Plaintext
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Copyright 1996 Free Software Foundation, Inc.
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This file is part of the GNU MP Library.
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The GNU MP Library is free software; you can redistribute it and/or modify
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it under the terms of the GNU Lesser General Public License as published by
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the Free Software Foundation; either version 2.1 of the License, or (at your
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option) any later version.
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The GNU MP Library is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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License for more details.
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You should have received a copy of the GNU Lesser General Public License
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along with the GNU MP Library; see the file COPYING.LIB. If not, write to
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the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
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02110-1301, USA.
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This directory contains mpn functions optimized for MIPS3. Example of
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processors that implement MIPS3 are R4000, R4400, R4600, R4700, and R8000.
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RELEVANT OPTIMIZATION ISSUES
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1. On the R4000 and R4400, branches, both the plain and the "likely" ones,
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take 3 cycles to execute. (The fastest possible loop will take 4 cycles,
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because of the delay insn.)
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On the R4600, branches takes a single cycle
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On the R8000, branches often take no noticable cycles, as they are
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executed in a separate function unit..
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2. The R4000 and R4400 have a load latency of 4 cycles.
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3. On the R4000 and R4400, multiplies take a data-dependent number of
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cycles, contrary to the SGI documentation. There seem to be 3 or 4
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possible latencies.
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4. The R1x000 processors can issue one floating-point operation, two integer
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operations, and one memory operation per cycle. The FPU has very short
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latencies, while the integer multiply unit is non-pipelined. We should
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therefore write fp based mpn_Xmul_1.
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STATUS
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Good...
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