118 lines
3.0 KiB
NASM
118 lines
3.0 KiB
NASM
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dnl Intel Pentium-4 mpn_rsh1add_n -- mpn (x+y)/2
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dnl Copyright 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
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dnl
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dnl This file is part of the GNU MP Library.
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dnl
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dnl The GNU MP Library is free software; you can redistribute it and/or
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dnl modify it under the terms of the GNU Lesser General Public License as
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dnl published by the Free Software Foundation; either version 2.1 of the
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dnl License, or (at your option) any later version.
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dnl
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dnl The GNU MP Library is distributed in the hope that it will be useful,
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dnl but WITHOUT ANY WARRANTY; without even the implied warranty of
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dnl MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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dnl Lesser General Public License for more details.
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dnl
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dnl You should have received a copy of the GNU Lesser General Public
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dnl License along with the GNU MP Library; see the file COPYING.LIB. If
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dnl not, write to the Free Software Foundation, Inc., 51 Franklin Street,
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dnl Fifth Floor, Boston, MA 02110-1301, USA.
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include(`../config.m4')
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C cycles/limb (approx)
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C dst!=src1,2 dst==src1 dst==src2
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C P4: 4.5 6.5 6.5
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C mp_limb_t mpn_rsh1add_n (mp_ptr wp, mp_srcptr xp, mp_srcptr yp,
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C mp_size_t size);
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C
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C The slightly strange combination of indexing and pointer incrementing
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C that's used seems to work best. Not sure why, but for instance leal
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C incrementing on %esi is a 1 or 2 cycle slowdown.
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C
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C The dependent chain is paddq combining the carry and next (shifted) part,
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C plus psrlq to move the new carry down. That, and just 4 mmx instructions
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C in total, makes 4 c/l the target speed, which is almost achieved for
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C separate src/dst but when src==dst the write combining anomalies slow it
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C down.
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defframe(PARAM_SIZE, 16)
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defframe(PARAM_YP, 12)
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defframe(PARAM_XP, 8)
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defframe(PARAM_WP, 4)
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dnl re-use parameter space
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define(SAVE_EBX,`PARAM_XP')
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define(SAVE_ESI,`PARAM_YP')
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TEXT
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ALIGN(8)
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PROLOGUE(mpn_rsh1add_n)
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deflit(`FRAME',0)
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movl PARAM_XP, %edx
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movl %ebx, SAVE_EBX
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movl PARAM_YP, %ebx
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movl %esi, SAVE_ESI
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movl PARAM_WP, %esi
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movd (%edx), %mm0 C xp[0]
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movd (%ebx), %mm1 C yp[0]
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movl PARAM_SIZE, %ecx
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movl (%edx), %eax C xp[0]
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addl (%ebx), %eax C xp[0]+yp[0]
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paddq %mm1, %mm0 C xp[0]+yp[0]
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leal (%esi,%ecx,4), %esi C wp end
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negl %ecx C -size
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psrlq $1, %mm0 C (xp[0]+yp[0])/2
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and $1, %eax C return value, rsh1 bit of xp[0]+yp[0]
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addl $1, %ecx C -(size-1)
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jz L(done)
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L(top):
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C eax return value
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C ebx yp end
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C ecx counter, limbs, -(size-1) to -1 inclusive
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C edx xp end
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C esi wp end
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C mm0 carry (32 bits)
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movd 4(%edx), %mm1 C xp[i+1]
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movd 4(%ebx), %mm2 C yp[i+1]
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leal 4(%edx), %edx
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leal 4(%ebx), %ebx
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paddq %mm2, %mm1 C xp[i+1]+yp[i+1]
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psllq $31, %mm1 C low bit at 31, further 32 above
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paddq %mm1, %mm0 C 31 and carry from prev add
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movd %mm0, -4(%esi,%ecx,4) C low ready to store dst[i]
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psrlq $32, %mm0 C high becomes new carry
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addl $1, %ecx
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jnz L(top)
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L(done):
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movd %mm0, -4(%esi) C dst[size-1]
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movl SAVE_EBX, %ebx
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movl SAVE_ESI, %esi
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emms
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ret
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EPILOGUE()
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