163 lines
3.8 KiB
NASM
163 lines
3.8 KiB
NASM
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dnl Alpha ev6 nails mpn_addmul_3.
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dnl Copyright 2002, 2006 Free Software Foundation, Inc.
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dnl
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dnl This file is part of the GNU MP Library.
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dnl
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dnl The GNU MP Library is free software; you can redistribute it and/or
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dnl modify it under the terms of the GNU Lesser General Public License as
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dnl published by the Free Software Foundation; either version 2.1 of the
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dnl License, or (at your option) any later version.
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dnl
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dnl The GNU MP Library is distributed in the hope that it will be useful,
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dnl but WITHOUT ANY WARRANTY; without even the implied warranty of
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dnl MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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dnl Lesser General Public License for more details.
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dnl
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dnl You should have received a copy of the GNU Lesser General Public
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dnl License along with the GNU MP Library; see the file COPYING.LIB. If
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dnl not, write to the Free Software Foundation, Inc., 51 Franklin Street,
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dnl Fifth Floor, Boston, MA 02110-1301, USA.
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dnl Runs at 3.0 cycles/limb. With unrolling, the ulimb load and the 3
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dnl bookkeeping increments and the `bis' that copies from r22 to r6 could be
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dnl removed and the instruction count reduced from 26 to to 21. We could
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dnl thereby probably reach 2 cycles/limb, the IMUL bandwidth.
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include(`../config.m4')
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dnl INPUT PARAMETERS
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define(`rp',`r16')
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define(`up',`r17')
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define(`n',`r18')
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define(`vp',`r19')
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dnl Useful register aliases
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define(`numb_mask',`r24')
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define(`ulimb',`r25')
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define(`rlimb',`r27')
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define(`m0a',`r0')
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define(`m0b',`r1')
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define(`m1a',`r2')
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define(`m1b',`r3')
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define(`m2a',`r20')
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define(`m2b',`r21')
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define(`acc0',`r4')
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define(`acc1',`r5')
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define(`acc2',`r22')
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define(`v0',`r6')
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define(`v1',`r7')
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define(`v2',`r23')
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dnl Used for temps: r8 r19 r28
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define(`NAIL_BITS',`GMP_NAIL_BITS')
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define(`NUMB_BITS',`GMP_NUMB_BITS')
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dnl This declaration is munged by configure
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NAILS_SUPPORT(3-63)
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ASM_START()
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PROLOGUE(mpn_addmul_3)
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lda numb_mask,-1(r31)
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srl numb_mask,NAIL_BITS,numb_mask
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ldq v0, 0(vp)
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ldq v1, 8(vp)
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ldq v2, 16(vp)
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bis r31, r31, acc0 C zero acc0
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sll v0,NAIL_BITS, v0
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bis r31, r31, acc1 C zero acc1
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sll v1,NAIL_BITS, v1
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bis r31, r31, acc2 C zero acc2
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sll v2,NAIL_BITS, v2
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bis r31, r31, r19
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ldq ulimb, 0(up)
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lda up, 8(up)
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mulq v0, ulimb, m0a C U1
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umulh v0, ulimb, m0b C U1
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mulq v1, ulimb, m1a C U1
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umulh v1, ulimb, m1b C U1
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lda n, -1(n)
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mulq v2, ulimb, m2a C U1
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umulh v2, ulimb, m2b C U1
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beq n, L(end) C U0
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ALIGN(16)
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L(top): bis r31, r31, r31 C nop
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ldq rlimb, 0(rp)
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ldq ulimb, 0(up)
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addq r19, acc0, acc0 C propagate nail
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lda rp, 8(rp)
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srl m0a,NAIL_BITS, r8 C U0
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lda up, 8(up)
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mulq v0, ulimb, m0a C U1
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addq r8, acc0, r19
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addq m0b, acc1, acc0
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umulh v0, ulimb, m0b C U1
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bis r31, r31, r31 C nop
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addq rlimb, r19, r19
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srl m1a,NAIL_BITS, r8 C U0
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bis r31, r31, r31 C nop
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mulq v1, ulimb, m1a C U1
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addq r8, acc0, acc0
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addq m1b, acc2, acc1
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umulh v1, ulimb, m1b C U1
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and r19,numb_mask, r28 C extract numb part
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bis r31, r31, r31 C nop
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srl m2a,NAIL_BITS, r8 C U0
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lda n, -1(n)
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mulq v2, ulimb, m2a C U1
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addq r8, acc1, acc1
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bis r31, m2b, acc2
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umulh v2, ulimb, m2b C U1
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srl r19,NUMB_BITS, r19 C extract nail part
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bis r31, r31, r31 C nop
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stq r28, -8(rp)
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bne n, L(top) C U0
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L(end): ldq rlimb, 0(rp)
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addq r19, acc0, acc0 C propagate nail
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lda rp, 8(rp)
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srl m0a,NAIL_BITS, r8 C U0
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addq r8, acc0, r19
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addq m0b, acc1, acc0
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addq rlimb, r19, r19
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srl m1a,NAIL_BITS, r8 C U0
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addq r8, acc0, acc0
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addq m1b, acc2, acc1
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and r19,numb_mask, r28 C extract limb
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srl m2a,NAIL_BITS, r8 C U0
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addq r8, acc1, acc1
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bis r31, m2b, acc2
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srl r19,NUMB_BITS, r19 C extract nail
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stq r28, -8(rp)
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addq r19, acc0, acc0 C propagate nail
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and acc0,numb_mask, r28
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stq r28, 0(rp)
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srl acc0,NUMB_BITS, r19
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addq r19, acc1, acc1
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and acc1,numb_mask, r28
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stq r28, 8(rp)
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srl acc1,NUMB_BITS, r19
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addq r19, acc2, m0a
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ret r31, (r26), 1
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EPILOGUE()
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ASM_END()
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