63 lines
2.4 KiB
Plaintext
63 lines
2.4 KiB
Plaintext
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Copyright 1996, 2001 Free Software Foundation, Inc.
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This file is part of the GNU MP Library.
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The GNU MP Library is free software; you can redistribute it and/or modify
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it under the terms of the GNU Lesser General Public License as published by
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the Free Software Foundation; either version 2.1 of the License, or (at your
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option) any later version.
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The GNU MP Library is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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License for more details.
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You should have received a copy of the GNU Lesser General Public License
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along with the GNU MP Library; see the file COPYING.LIB. If not, write to
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the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
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02110-1301, USA.
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This directory contains mpn functions for various SPARC chips. Code that
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runs only on version 8 SPARC implementations, is in the v8 subdirectory.
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RELEVANT OPTIMIZATION ISSUES
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Load and Store timing
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On most early SPARC implementations, the ST instructions takes multiple
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cycles, while a STD takes just a single cycle more than an ST. For the CPUs
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in SPARCstation I and II, the times are 3 and 4 cycles, respectively.
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Therefore, combining two ST instructions into a STD when possible is a
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significant optimization.
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Later SPARC implementations have single cycle ST.
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For SuperSPARC, we can perform just one memory instruction per cycle, even
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if up to two integer instructions can be executed in its pipeline. For
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programs that perform so many memory operations that there are not enough
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non-memory operations to issue in parallel with all memory operations, using
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LDD and STD when possible helps.
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UltraSPARC-1/2 has very slow integer multiplication. In the v9 subdirectory,
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we therefore use floating-point multiplication.
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STATUS
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1. On a SuperSPARC, mpn_lshift and mpn_rshift run at 3 cycles/limb, or 2.5
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cycles/limb asymptotically. We could optimize speed for special counts
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by using ADDXCC.
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2. On a SuperSPARC, mpn_add_n and mpn_sub_n runs at 2.5 cycles/limb, or 2
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cycles/limb asymptotically.
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3. mpn_mul_1 runs at what is believed to be optimal speed.
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4. On SuperSPARC, mpn_addmul_1 and mpn_submul_1 could both be improved by a
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cycle by avoiding one of the add instructions. See a29k/addmul_1.
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The speed of the code for other SPARC implementations is uncertain.
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