117 lines
3.2 KiB
Plaintext
117 lines
3.2 KiB
Plaintext
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Copyright 2000, 2001 Free Software Foundation, Inc.
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This file is part of the GNU MP Library.
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The GNU MP Library is free software; you can redistribute it and/or modify
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it under the terms of the GNU Lesser General Public License as published by
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the Free Software Foundation; either version 2.1 of the License, or (at your
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option) any later version.
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The GNU MP Library is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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License for more details.
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You should have received a copy of the GNU Lesser General Public License
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along with the GNU MP Library; see the file COPYING.LIB. If not, write to
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the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
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02110-1301, USA.
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INTEL P6 MPN SUBROUTINES
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This directory contains code optimized for Intel P6 class CPUs, meaning
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PentiumPro, Pentium II and Pentium III. The mmx and p3mmx subdirectories
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have routines using MMX instructions.
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STATUS
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Times for the loops, with all code and data in L1 cache, are as follows.
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Some of these might be able to be improved.
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cycles/limb
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mpn_add_n/sub_n 3.7
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mpn_copyi 0.75
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mpn_copyd 1.75 (or 0.75 if no overlap)
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mpn_divrem_1 39.0
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mpn_mod_1 21.5
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mpn_divexact_by3 8.5
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mpn_mul_1 5.5
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mpn_addmul/submul_1 6.35
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mpn_l/rshift 2.5
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mpn_mul_basecase 8.2 cycles/crossproduct (approx)
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mpn_sqr_basecase 4.0 cycles/crossproduct (approx)
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or 7.75 cycles/triangleproduct (approx)
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Pentium II and III have MMX and get the following improvements.
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mpn_divrem_1 25.0 integer part, 17.5 fractional part
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mpn_l/rshift 1.75
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NOTES
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Write-allocate L1 data cache means prefetching of destinations is unnecessary.
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Mispredicted branches have a penalty of between 9 and 15 cycles, and even up
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to 26 cycles depending how far speculative execution has gone. The 9 cycle
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minimum penalty comes from the issue pipeline being 9 stages.
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A copy with rep movs seems to copy 16 bytes at a time, since speeds for 4,
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5, 6 or 7 limb operations are all the same. The 0.75 cycles/limb would be 3
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cycles per 16 byte block.
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CODING
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Instructions in general code have been shown grouped if they can execute
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together, which means up to three instructions with no successive
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dependencies, and with only the first being a multiple micro-op.
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P6 has out-of-order execution, so the groupings are really only showing
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dependent paths where some shuffling might allow some latencies to be
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hidden.
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REFERENCES
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"Intel Architecture Optimization Reference Manual", 1999, revision 001 dated
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02/99, order number 245127 (order number 730795-001 is in the document too).
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Available on-line:
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http://download.intel.com/design/PentiumII/manuals/245127.htm
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"Intel Architecture Optimization Manual", 1997, order number 242816. This
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is an older document mostly about P5 and not as good as the above.
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Available on-line:
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http://download.intel.com/design/PentiumII/manuals/242816.htm
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----------------
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Local variables:
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mode: text
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fill-column: 76
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End:
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