117 lines
5.0 KiB
Plaintext
117 lines
5.0 KiB
Plaintext
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Copyright 1997, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
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This file is part of the GNU MP Library.
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The GNU MP Library is free software; you can redistribute it and/or modify
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it under the terms of the GNU Lesser General Public License as published by
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the Free Software Foundation; either version 2.1 of the License, or (at your
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option) any later version.
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The GNU MP Library is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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License for more details.
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You should have received a copy of the GNU Lesser General Public License
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along with the GNU MP Library; see the file COPYING.LIB. If not, write to
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the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
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02110-1301, USA.
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This directory contains mpn functions for 64-bit V9 SPARC
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RELEVANT OPTIMIZATION ISSUES
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Notation:
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IANY = shift/add/sub/logical/sethi
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IADDLOG = add/sub/logical/sethi
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MEM = ld*/st*
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FA = fadd*/fsub*/f*to*/fmov*
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FM = fmul*
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UltraSPARC can issue four instructions per cycle, with these restrictions:
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* Two IANY instructions, but only one of these may be a shift. If there is a
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shift and an IANY instruction, the shift must precede the IANY instruction.
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* One FA.
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* One FM.
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* One branch.
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* One MEM.
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* IANY/IADDLOG/MEM must be insn 1, 2, or 3 in an issue bundle. Taken branches
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should not be in slot 4, since that makes the delay insn come from separate
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bundle.
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* If two IANY/IADDLOG instructions are to be executed in the same cycle and one
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of these is setting the condition codes, that instruction must be the second
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one.
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To summarize, ignoring branches, these are the bundles that can reach the peak
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execution speed:
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insn1 iany iany mem iany iany mem iany iany mem
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insn2 iaddlog mem iany mem iaddlog iany mem iaddlog iany
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insn3 mem iaddlog iaddlog fa fa fa fm fm fm
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insn4 fa/fm fa/fm fa/fm fm fm fm fa fa fa
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The 64-bit integer multiply instruction mulx takes from 5 cycles to 35 cycles,
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depending on the position of the most significant bit of the first source
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operand. When used for 32x32->64 multiplication, it needs 20 cycles.
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Furthermore, it stalls the processor while executing. We stay away from that
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instruction, and instead use floating-point operations.
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Floating-point add and multiply units are fully pipelined. The latency for
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UltraSPARC-1/2 is 3 cycles and for UltraSPARC-3 it is 4 cycles.
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Integer conditional move instructions cannot dual-issue with other integer
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instructions. No conditional move can issue 1-5 cycles after a load. (This
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might have been fixed for UltraSPARC-3.)
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The UltraSPARC-3 pipeline is very simular to he one of UltraSPARC-1/2 , but is
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somewhat slower. Branches execute slower, and there may be other new stalls.
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But integer multiply doesn't stall the entire CPU and also has a much lower
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latency. But it's still not pipelined, and thus useless for our needs.
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STATUS
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* mpn_lshift, mpn_rshift: The current code runs at 2.0 cycles/limb on
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UltraSPARC-1/2 and 2.65 on UltraSPARC-3. For UltraSPARC-1/2, the IEU0
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functional unit is saturated with shifts.
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* mpn_add_n, mpn_sub_n: The current code runs at 4 cycles/limb on
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UltraSPARC-1/2 and 4.5 cycles/limb on UltraSPARC-3. The 4 instruction
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recurrency is the speed limiter.
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* mpn_addmul_1: The current code runs at 14 cycles/limb asymptotically on
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UltraSPARC-1/2 and 17.5 cycles/limb on UltraSPARC-3. On UltraSPARC-1/2, the
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code sustains 4 instructions/cycle. It might be possible to invent a better
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way of summing the intermediate 49-bit operands, but it is unlikely that it
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will save enough instructions to save an entire cycle.
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The load-use of the u operand is not enough scheduled for good L2 cache
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performance. The UltraSPARC-1/2 L1 cache is direct mapped, and since we use
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temporary stack slots that will conflict with the u and r operands, we miss
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to L2 very often. The load-use of the std/ldx pairs via the stack are
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perhaps over-scheduled.
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It would be possible to save two instructions: (1) The mov could be avoided
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if the std/ldx were less scheduled. (2) The ldx of the r operand could be
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split into two ld instructions, saving the shifts/masks.
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It should be possible to reach 14 cycles/limb for UltraSPARC-3 if the fp
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operations where rescheduled for this processor's 4-cycle latency.
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* mpn_mul_1: The current code is a straightforward edit of the mpn_addmul_1
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code. It would be possible to shave one or two cycles from it, with some
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labour.
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* mpn_submul_1: Simpleminded code just calling mpn_mul_1 + mpn_sub_n. This
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means that it runs at 18 cycles/limb on UltraSPARC-1/2 and 23 cycles/limb on
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UltraSPARC-3. It would be possible to either match the mpn_addmul_1
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performance, or in the worst case use one more instruction group.
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* US1/US2 cache conflict resolving. The direct mapped L1 date cache of US1/US2
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is a problem for mul_1, addmul_1 (and a prospective submul_1). We should
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allocate a larger cache area, and put the stack temp area in a place that
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doesn't cause cache conflicts.
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