2013-08-04 18:17:37 -04:00
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; PROLOGUE(mpn_karaadd)
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2012-11-25 17:13:44 -05:00
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; mpn_karaadd
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;
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; Copyright 2011 The Code Cavern
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;
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; Windows Conversion Copyright 2008 Brian Gladman
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;
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; This file is part of the MPIR Library.
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;
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; The MPIR Library is free software; you can redistribute it and/or modify
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; it under the terms of the GNU Lesser General Public License as published
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; by the Free Software Foundation; either version 2.1 of the License, or (at
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; your option) any later version.
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;
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; The MPIR Library is distributed in the hope that it will be useful, but
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; WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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; License for more details.
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;
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; You should have received a copy of the GNU Lesser General Public License
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; along with the MPIR Library; see the file COPYING.LIB. If not, write
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; to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
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; Boston, MA 02110-1301, USA.
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;
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; void mpn_karaadd(mp_ptr, mp_ptr, mp_size_t)
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; rax rdi rsi rdx
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; rax rcx rdx r8
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%include "yasm_mac.inc"
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%define reg_save_list rbx, rbp, rsi, rdi, r12, r13, r14, r15
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BITS 64
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TEXT
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; requires n >= 8
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FRAME_PROC mpn_karaadd, 1, reg_save_list
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mov rdi, rcx
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mov rsi, rdx
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mov rdx, r8
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mov [rsp], rdx
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;rp is rdi
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;tp is rsi
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;n is rdx and put it on the stack
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shr rdx, 1
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;n2 is rdx
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lea rcx, [rdx+rdx*1]
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; 2*n2 is rcx
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; L is rdi
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; H is rbp
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; tp is rsi
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lea rbp, [rdi+rcx*8]
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xor rax, rax
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xor rbx, rbx
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; rax rbx are the carrys
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lea rdi, [rdi+rdx*8-24]
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lea rsi, [rsi+rdx*8-24]
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lea rbp, [rbp+rdx*8-24]
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mov ecx, 3
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sub rcx, rdx
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mov edx, 3
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align 16
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lp: bt rbx, 2
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mov r8, [rdi+rdx*8]
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adc r8, [rbp+rcx*8]
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mov r12, r8
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mov r9, [rdi+rdx*8+8]
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adc r9, [rbp+rcx*8+8]
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mov r10, [rdi+rdx*8+16]
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adc r10, [rbp+rcx*8+16]
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mov r11, [rdi+rdx*8+24]
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adc r11, [rbp+rcx*8+24]
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rcl rbx, 1
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bt rax, 1
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mov r15, r11
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adc r8, [rdi+rcx*8]
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mov r13, r9
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adc r9, [rdi+rcx*8+8]
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mov r14, r10
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adc r10, [rdi+rcx*8+16]
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adc r11, [rdi+rcx*8+24]
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rcl rax, 1
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bt rbx, 2
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adc r12, [rbp+rdx*8]
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adc r13, [rbp+rdx*8+8]
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adc r14, [rbp+rdx*8+16]
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adc r15, [rbp+rdx*8+24]
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rcl rbx, 1
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bt rax, 1
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adc r8, [rsi+rcx*8]
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adc r9, [rsi+rcx*8+8]
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adc r10, [rsi+rcx*8+16]
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adc r11, [rsi+rcx*8+24]
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mov [rdi+rdx*8+16], r10
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mov [rdi+rdx*8+24], r11
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rcl rax, 1
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bt rbx, 2
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mov [rdi+rdx*8], r8
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mov [rdi+rdx*8+8], r9
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adc r12, [rsi+rdx*8]
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adc r13, [rsi+rdx*8+8]
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adc r14, [rsi+rdx*8+16]
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adc r15, [rsi+rdx*8+24]
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rcl rbx, 1
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add rdx, 4
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mov [rbp+rcx*8], r12
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mov [rbp+rcx*8+8], r13
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mov [rbp+rcx*8+16], r14
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mov [rbp+rcx*8+24], r15
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add rcx, 4
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jnc lp
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cmp rcx, 2
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jg case0
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jz case1
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jp case2
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case3:
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bt rbx, 2
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mov r8, [rdi+rdx*8]
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adc r8, [rbp]
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mov r12, r8
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mov r9, [rdi+rdx*8+8]
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adc r9, [rbp+8]
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mov r10, [rdi+rdx*8+16]
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adc r10, [rbp+16]
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rcl rbx, 1
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bt rax, 1
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adc r8, [rdi]
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mov r13, r9
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adc r9, [rdi+8]
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mov r14, r10
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adc r10, [rdi+16]
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rcl rax, 1
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bt rbx, 2
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adc r12, [rbp+rdx*8]
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adc r13, [rbp+rdx*8+8]
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adc r14, [rbp+rdx*8+16]
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rcl rbx, 1
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bt rax, 1
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adc r8, [rsi]
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adc r9, [rsi+8]
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adc r10, [rsi+16]
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mov [rdi+rdx*8+16], r10
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rcl rax, 1
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bt rbx, 2
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mov [rdi+rdx*8], r8
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mov [rdi+rdx*8+8], r9
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adc r12, [rsi+rdx*8]
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adc r13, [rsi+rdx*8+8]
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adc r14, [rsi+rdx*8+16]
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rcl rbx, 1
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add rdx, 3
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mov [rbp], r12
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mov [rbp+8], r13
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mov [rbp+16], r14
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jmp fin
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case2:
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bt rbx, 2
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mov r8, [rdi+rdx*8]
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adc r8, [rbp+8]
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mov r12, r8
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mov r9, [rdi+rdx*8+8]
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adc r9, [rbp+16]
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rcl rbx, 1
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bt rax, 1
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adc r8, [rdi+8]
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mov r13, r9
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adc r9, [rdi+16]
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rcl rax, 1
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bt rbx, 2
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adc r12, [rbp+rdx*8]
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adc r13, [rbp+rdx*8+8]
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rcl rbx, 1
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bt rax, 1
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adc r8, [rsi+8]
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adc r9, [rsi+16]
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rcl rax, 1
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bt rbx, 2
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mov [rdi+rdx*8], r8
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mov [rdi+rdx*8+8], r9
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adc r12, [rsi+rdx*8]
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adc r13, [rsi+rdx*8+8]
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rcl rbx, 1
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add rdx, 2
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mov [rbp+8], r12
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mov [rbp+16], r13
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jmp fin
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case1:
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bt rbx, 2
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mov r8, [rdi+rdx*8]
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adc r8, [rbp+16]
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mov r12, r8
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rcl rbx, 1
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bt rax, 1
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adc r8, [rdi+16]
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rcl rax, 1
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bt rbx, 2
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adc r12, [rbp+rdx*8]
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rcl rbx, 1
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bt rax, 1
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adc r8, [rsi+16]
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rcl rax, 1
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bt rbx, 2
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mov [rdi+rdx*8], r8
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adc r12, [rsi+rdx*8]
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rcl rbx, 1
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inc rdx
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mov [rbp+rcx*8], r12
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fin: mov rcx, 3
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case0:
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mov r8, [rsp]
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bt r8, 0
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jnc notodd
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xor r10, r10
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mov r8, [rbp+rdx*8]
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mov r9, [rbp+rdx*8+8]
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add r8, [rsi+rdx*8]
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adc r9, [rsi+rdx*8+8]
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rcl r10, 1
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add [rbp+24], r8
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adc [rbp+32], r9
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adc [rbp+40], r10
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l7: adc qword[rbp+rcx*8+24], 0
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inc rcx
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jc l7
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mov rcx, 3
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notodd: and rax, 3
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popcnt r8, rax
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bt rbx, 2
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adc r8, 0
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adc [rdi+rdx*8], r8
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l1: adc qword[rdi+rdx*8+8], 0
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inc rdx
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jc l1
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and rbx, 7
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popcnt r8, rbx
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add [rbp+24], r8
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l2: adc qword[rbp+rcx*8+8], 0
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inc rcx
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jc l2
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END_PROC reg_save_list
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end
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