275 lines
7.6 KiB
NASM
275 lines
7.6 KiB
NASM
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dnl Alpha ev6 mpn_add_n -- Add two limb vectors of the same length > 0 and
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dnl store sum in a third limb vector.
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dnl Copyright 2000, 2003, 2005 Free Software Foundation, Inc.
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dnl This file is part of the GNU MP Library.
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dnl The GNU MP Library is free software; you can redistribute it and/or modify
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dnl it under the terms of the GNU Lesser General Public License as published
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dnl by the Free Software Foundation; either version 2.1 of the License, or (at
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dnl your option) any later version.
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dnl The GNU MP Library is distributed in the hope that it will be useful, but
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dnl WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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dnl or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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dnl License for more details.
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dnl You should have received a copy of the GNU Lesser General Public License
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dnl along with the GNU MP Library; see the file COPYING.LIB. If not, write
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dnl to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
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dnl Boston, MA 02110-1301, USA.
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include(`../config.m4')
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C cycles/limb
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C EV4: ?
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C EV5: 5.4
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C EV6: 2.125
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C INPUT PARAMETERS
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C rp r16
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C up r17
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C vp r18
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C n r19
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C cy r20 (for mpn_add_nc)
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C TODO
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C Finish cleaning up cy registers r22, r23 (make them use cy0/cy1)
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C Use multi-pronged feed-in.
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C Perform additional micro-tuning
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C This code was written in cooperation with ev6 pipeline expert Steve Root.
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C Pair loads and stores where possible
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C Store pairs oct-aligned where possible (didn't need it here)
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C Stores are delayed every third cycle
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C Loads and stores are delayed by fills
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C U stays still, put code there where possible (note alternation of U1 and U0)
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C L moves because of loads and stores
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C Note dampers in L to limit damage
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C This odd-looking optimization expects that were having random bits in our
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C data, so that a pure zero result is unlikely. so we penalize the unlikely
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C case to help the common case.
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define(`u0', `r0') define(`u1', `r3')
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define(`v0', `r1') define(`v1', `r4')
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define(`cy0', `r20') define(`cy1', `r21')
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MULFUNC_PROLOGUE(mpn_add_n mpn_add_nc)
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ASM_START()
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PROLOGUE(mpn_add_nc)
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br r31, $entry
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EPILOGUE()
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PROLOGUE(mpn_add_n)
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bis r31, r31, cy0 C clear carry in
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$entry: cmpult r19, 5, r22 C L1 move counter
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ldq u1, 0(r17) C L0 get next ones
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ldq v1, 0(r18) C L1
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bne r22, $Lsmall
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ldq u0, 8(r17) C L0 get next ones
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ldq v0, 8(r18) C L1
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addq u1, v1, r5 C U0 add two data
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cmpult r5, v1, r23 C U0 did it carry
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ldq u1, 16(r17) C L0 get next ones
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ldq v1, 16(r18) C L1
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addq u0, v0, r8 C U1 add two data
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addq r5, cy0, r5 C U0 carry in
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cmpult r8, v0, r22 C U1 did it carry
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beq r5, $fix5f C U0 fix exact zero
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$ret5f: ldq u0, 24(r17) C L0 get next ones
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ldq v0, 24(r18) C L1
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addq r8, r23, r8 C U1 carry from last
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addq u1, v1, r7 C U0 add two data
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beq r8, $fix6f C U1 fix exact zero
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$ret6f: cmpult r7, v1, r23 C U0 did it carry
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ldq u1, 32(r17) C L0 get next ones
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ldq v1, 32(r18) C L1
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lda r17, 40(r17) C L0 move pointer
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lda r18, 40(r18) C L1 move pointer
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lda r16, -8(r16)
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lda r19, -13(r19) C L1 move counter
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blt r19, $Lend C U1 loop control
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C Main loop. 8-way unrolled.
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ALIGN(16)
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$Loop: addq u0, v0, r2 C U1 add two data
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addq r7, r22, r7 C U0 add in carry
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stq r5, 8(r16) C L0 put an answer
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stq r8, 16(r16) C L1 pair
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cmpult r2, v0, cy1 C U1 did it carry
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beq r7, $fix7 C U0 fix exact 0
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$ret7: ldq u0, 0(r17) C L0 get next ones
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ldq v0, 0(r18) C L1
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bis r31, r31, r31 C L damp out
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addq r2, r23, r2 C U1 carry from last
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bis r31, r31, r31 C L moves in L !
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addq u1, v1, r5 C U0 add two data
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beq r2, $fix0 C U1 fix exact zero
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$ret0: cmpult r5, v1, cy0 C U0 did it carry
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ldq u1, 8(r17) C L0 get next ones
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ldq v1, 8(r18) C L1
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addq u0, v0, r8 C U1 add two data
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addq r5, cy1, r5 C U0 carry from last
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stq r7, 24(r16) C L0 store pair
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stq r2, 32(r16) C L1
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cmpult r8, v0, r22 C U1 did it carry
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beq r5, $fix1 C U0 fix exact zero
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$ret1: ldq u0, 16(r17) C L0 get next ones
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ldq v0, 16(r18) C L1
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lda r16, 64(r16) C L0 move pointer
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addq r8, cy0, r8 C U1 carry from last
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lda r19, -8(r19) C L1 move counter
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addq u1, v1, r7 C U0 add two data
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beq r8, $fix2 C U1 fix exact zero
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$ret2: cmpult r7, v1, r23 C U0 did it carry
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ldq u1, 24(r17) C L0 get next ones
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ldq v1, 24(r18) C L1
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addq u0, v0, r2 C U1 add two data
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addq r7, r22, r7 C U0 add in carry
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stq r5, -24(r16) C L0 put an answer
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stq r8, -16(r16) C L1 pair
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cmpult r2, v0, cy1 C U1 did it carry
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beq r7, $fix3 C U0 fix exact 0
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$ret3: ldq u0, 32(r17) C L0 get next ones
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ldq v0, 32(r18) C L1
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bis r31, r31, r31 C L damp out
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addq r2, r23, r2 C U1 carry from last
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bis r31, r31, r31 C L moves in L !
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addq u1, v1, r5 C U0 add two data
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beq r2, $fix4 C U1 fix exact zero
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$ret4: cmpult r5, v1, cy0 C U0 did it carry
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ldq u1, 40(r17) C L0 get next ones
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ldq v1, 40(r18) C L1
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addq u0, v0, r8 C U1 add two data
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addq r5, cy1, r5 C U0 carry from last
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stq r7, -8(r16) C L0 store pair
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stq r2, 0(r16) C L1
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cmpult r8, v0, r22 C U1 did it carry
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beq r5, $fix5 C U0 fix exact zero
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$ret5: ldq u0, 48(r17) C L0 get next ones
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ldq v0, 48(r18) C L1
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ldl r31, 256(r17) C L0 prefetch
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addq r8, cy0, r8 C U1 carry from last
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ldl r31, 256(r18) C L1 prefetch
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addq u1, v1, r7 C U0 add two data
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beq r8, $fix6 C U1 fix exact zero
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$ret6: cmpult r7, v1, r23 C U0 did it carry
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ldq u1, 56(r17) C L0 get next ones
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ldq v1, 56(r18) C L1
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lda r17, 64(r17) C L0 move pointer
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bis r31, r31, r31 C U
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lda r18, 64(r18) C L1 move pointer
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bge r19, $Loop C U1 loop control
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C ==== main loop end
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$Lend: addq u0, v0, r2 C U1 add two data
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addq r7, r22, r7 C U0 add in carry
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stq r5, 8(r16) C L0 put an answer
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stq r8, 16(r16) C L1 pair
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cmpult r2, v0, cy1 C U1 did it carry
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beq r7, $fix7c C U0 fix exact 0
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$ret7c: addq r2, r23, r2 C U1 carry from last
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addq u1, v1, r5 C U0 add two data
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beq r2, $fix0c C U1 fix exact zero
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$ret0c: cmpult r5, v1, cy0 C U0 did it carry
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addq r5, cy1, r5 C U0 carry from last
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stq r7, 24(r16) C L0 store pair
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stq r2, 32(r16) C L1
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beq r5, $fix1c C U0 fix exact zero
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$ret1c: stq r5, 40(r16) C L0 put an answer
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lda r16, 48(r16) C L0 move pointer
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lda r19, 8(r19)
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beq r19, $Lret
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ldq u1, 0(r17)
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ldq v1, 0(r18)
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$Lsmall:
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lda r19, -1(r19)
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beq r19, $Lend0
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ALIGN(8)
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$Loop0: addq u1, v1, r2 C main add
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cmpult r2, v1, r8 C compute cy from last add
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ldq u1, 8(r17)
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ldq v1, 8(r18)
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addq r2, cy0, r5 C carry add
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lda r17, 8(r17)
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lda r18, 8(r18)
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stq r5, 0(r16)
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cmpult r5, r2, cy0 C compute cy from last add
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lda r19, -1(r19) C decr loop cnt
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bis r8, cy0, cy0 C combine cy from the two adds
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lda r16, 8(r16)
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bne r19, $Loop0
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$Lend0: addq u1, v1, r2 C main add
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addq r2, cy0, r5 C carry add
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cmpult r2, v1, r8 C compute cy from last add
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cmpult r5, r2, cy0 C compute cy from last add
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stq r5, 0(r16)
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bis r8, cy0, r0 C combine cy from the two adds
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ret r31,(r26),1
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ALIGN(8)
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$Lret: lda r0, 0(cy0) C copy carry into return register
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ret r31,(r26),1
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$fix5f: bis r23, cy0, r23 C bring forward carry
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br r31, $ret5f
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$fix6f: bis r22, r23, r22 C bring forward carry
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br r31, $ret6f
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$fix0: bis cy1, r23, cy1 C bring forward carry
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br r31, $ret0
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$fix1: bis cy0, cy1, cy0 C bring forward carry
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br r31, $ret1
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$fix2: bis r22, cy0, r22 C bring forward carry
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br r31, $ret2
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$fix3: bis r23, r22, r23 C bring forward carry
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br r31, $ret3
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$fix4: bis cy1, r23, cy1 C bring forward carry
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br r31, $ret4
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$fix5: bis cy1, cy0, cy0 C bring forward carry
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br r31, $ret5
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$fix6: bis r22, cy0, r22 C bring forward carry
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br r31, $ret6
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$fix7: bis r23, r22, r23 C bring forward carry
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br r31, $ret7
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$fix0c: bis cy1, r23, cy1 C bring forward carry
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br r31, $ret0c
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$fix1c: bis cy0, cy1, cy0 C bring forward carry
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br r31, $ret1c
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$fix7c: bis r23, r22, r23 C bring forward carry
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br r31, $ret7c
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EPILOGUE()
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ASM_END()
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