Check for AESNI & PCLMUL presence/usability
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20
configure.ac
20
configure.ac
@ -211,9 +211,6 @@ AX_CHECK_COMPILE_FLAG([-Wwrite-strings], [CFLAGS="$CFLAGS -Wwrite-strings"])
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AX_CHECK_COMPILE_FLAG([-Wdiv-by-zero], [CFLAGS="$CFLAGS -Wdiv-by-zero"])
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AX_CHECK_COMPILE_FLAG([-Wsometimes-uninitialized], [CFLAGS="$CFLAGS -Wsometimes-uninitialized"])
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AC_MSG_CHECKING([Checking if we can compile for westmere])
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AX_CHECK_COMPILE_FLAG([-march=westmere $CFLAGS], [CFLAGS="-march=westmere $CFLAGS"])
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AC_ARG_VAR([CWFLAGS], [define to compilation flags for generating extra warnings])
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AX_CHECK_COMPILE_FLAG([$CWFLAGS -Wall], [CWFLAGS="$CWFLAGS -Wall"])
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@ -301,6 +298,23 @@ AS_IF([test "x$EMSCRIPTEN" = "x"],[
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[AC_MSG_RESULT(yes)
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AC_DEFINE([HAVE_TMMINTRIN_H], [1], [ssse3 is available])],
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[AC_MSG_RESULT(no)])
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AC_MSG_CHECKING(for AESNI instructions set and PCLMULQDQ)
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AC_COMPILE_IFELSE([AC_LANG_PROGRAM([[
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#pragma GCC target("aes")
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#pragma GCC target("pclmul")
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#ifndef __AES__
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# define __AES__
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#endif
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#ifndef __PCLMUL__
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# define __PCLMUL__
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#endif
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#include <wmmintrin.h>
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]], [[ __m128i x = _mm_aesimc_si128(_mm_setzero_si128());
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__m128i y = _mm_clmulepi64_si128(_mm_setzero_si128(), _mm_setzero_si128(), 0);]])],
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[AC_MSG_RESULT(yes)
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AC_DEFINE([HAVE_WMMINTRIN_H], [1], [aesni is available])],
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[AC_MSG_RESULT(no)])
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])
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AC_CHECK_HEADERS([sys/mman.h])
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@ -3,6 +3,23 @@
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* AES256-GCM, based on original code by Romain Dolbeau
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*/
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#pragma GCC target("sse")
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#pragma GCC target("sse2")
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#pragma GCC target("ssse3")
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#pragma GCC target("sse4.1")
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#pragma GCC target("aes")
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#pragma GCC target("pclmul")
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#ifndef __SSE4_1__
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# define __SSE4_1__
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#endif
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#ifndef __AES__
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# define __AES__
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#endif
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#ifndef __PCLMUL__
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# define __PCLMUL__
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#endif
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#include <immintrin.h>
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#include <stdint.h>
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#include <stdlib.h>
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@ -20,6 +20,12 @@ int sodium_runtime_has_sse2(void);
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SODIUM_EXPORT
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int sodium_runtime_has_sse3(void);
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SODIUM_EXPORT
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int sodium_runtime_has_pclmul(void);
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SODIUM_EXPORT
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int sodium_runtime_has_aesni(void);
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#ifdef __cplusplus
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}
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#endif
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@ -10,12 +10,16 @@ typedef struct CPUFeatures_ {
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int has_neon;
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int has_sse2;
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int has_sse3;
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int has_pclmul;
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int has_aesni;
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} CPUFeatures;
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static CPUFeatures _cpu_features;
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#define CPUID_SSE2 0x04000000
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#define CPUIDECX_SSE3 0x00000001
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#define CPUIDECX_PCLMUL 0x00000002
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#define CPUIDECX_AESNI 0x02000000
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static int
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_sodium_runtime_arm_cpu_features(CPUFeatures * const cpu_features)
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@ -104,6 +108,14 @@ _sodium_runtime_intel_cpu_features(CPUFeatures * const cpu_features)
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cpu_features->has_sse3 = ((cpu_info[2] & CPUIDECX_SSE3) != 0x0);
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#endif
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#ifndef HAVE_WMMINTRIN_H
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cpu_features->has_pclmul = 0;
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cpu_features->has_aesni = 0;
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#else
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cpu_features->has_pclmul = ((cpu_info[2] & CPUIDECX_PCLMUL) != 0x0);
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cpu_features->has_aesni = ((cpu_info[2] & CPUIDECX_AESNI) != 0x0);
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#endif
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return 0;
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}
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@ -133,3 +145,13 @@ int
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sodium_runtime_has_sse3(void) {
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return _cpu_features.has_sse3;
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}
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int
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sodium_runtime_has_pclmul(void) {
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return _cpu_features.has_pclmul;
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}
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int
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sodium_runtime_has_aesni(void) {
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return _cpu_features.has_aesni;
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}
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