Check the extended control register to see if AVX is actually usable
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@ -1,4 +1,6 @@
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#include <stddef.h>
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#include <stdint.h>
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#ifdef HAVE_ANDROID_GETCPUFEATURES
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#ifdef HAVE_ANDROID_GETCPUFEATURES
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# include <cpu-features.h>
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# include <cpu-features.h>
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#endif
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#endif
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@ -26,6 +28,11 @@ static CPUFeatures _cpu_features;
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#define CPUIDECX_AVX 0x10000000
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#define CPUIDECX_AVX 0x10000000
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#define CPUIDECX_PCLMUL 0x00000002
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#define CPUIDECX_PCLMUL 0x00000002
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#define CPUIDECX_AESNI 0x02000000
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#define CPUIDECX_AESNI 0x02000000
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#define CPUIDECX_XSAVE 0x04000000
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#define CPUIDECX_OSXSAVE 0x08000000
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#define XCR0_SSE 0x00000002
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#define XCR0_AVX 0x00000004
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static int
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static int
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_sodium_runtime_arm_cpu_features(CPUFeatures * const cpu_features)
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_sodium_runtime_arm_cpu_features(CPUFeatures * const cpu_features)
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@ -130,11 +137,21 @@ _sodium_runtime_intel_cpu_features(CPUFeatures * const cpu_features)
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cpu_features->has_sse41 = 0;
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cpu_features->has_sse41 = 0;
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#endif
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#endif
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cpu_features->has_avx = 0;
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#if defined(HAVE_AVXINTRIN_H) || \
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#if defined(HAVE_AVXINTRIN_H) || \
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(defined(_MSC_VER) && (defined(_M_X64) || defined(_M_AMD64) || defined(_M_IX86)))
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(defined(_MSC_VER) && (defined(_M_X64) || defined(_M_AMD64) || defined(_M_IX86)))
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# ifdef HAVE_AMD64_ASM
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if ((cpu_info[2] & (CPUIDECX_AVX | CPUIDECX_XSAVE | CPUIDECX_OSXSAVE))
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== (CPUIDECX_AVX | CPUIDECX_XSAVE | CPUIDECX_OSXSAVE)) {
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uint32_t eax, edx;
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__asm__ __volatile__ (".byte 0x0f, 0x01, 0xd0" /* XGETBV */
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: "=a"(eax), "=d"(edx)
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: "c"((uint32_t) 0U));
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if ((eax & (XCR0_SSE | XCR0_AVX)) == (XCR0_SSE | XCR0_AVX)) {
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cpu_features->has_avx = ((cpu_info[2] & CPUIDECX_AVX) != 0x0);
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cpu_features->has_avx = ((cpu_info[2] & CPUIDECX_AVX) != 0x0);
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#else
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}
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cpu_features->has_avx = 0;
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}
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# endif
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#endif
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#endif
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#if defined(HAVE_WMMINTRIN_H) || \
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#if defined(HAVE_WMMINTRIN_H) || \
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